Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1309297 > unrolled thread
| Started by | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| First post | 2016-01-14 15:10 +0100 |
| Last post | 2016-01-15 10:10 +0100 |
| Articles | 2 — 2 participants |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
Re: [PATCH V4 06/16] soc: tegra: pmc: Wait for powergate state to change Thierry Reding <thierry.reding@gmail.com> - 2016-01-14 15:10 +0100
Re: [PATCH V4 06/16] soc: tegra: pmc: Wait for powergate state to change Jon Hunter <jonathanh@nvidia.com> - 2016-01-15 10:10 +0100
| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-01-14 15:10 +0100 |
| Subject | Re: [PATCH V4 06/16] soc: tegra: pmc: Wait for powergate state to change |
| Message-ID | <qQQL8-8bA-7@gated-at.bofh.it> |
[Multipart message — attachments visible in raw view] — view raw
On Fri, Dec 04, 2015 at 02:57:07PM +0000, Jon Hunter wrote:
> Currently, the function tegra_powergate_set() simply sets the desired
> powergate state but does not wait for the state to change. In most cases
> we should wait for the state to change before proceeding. Currently, there
> is a case for tegra114 and tegra124 devices where we do not wait when
> starting the secondary CPU as this is not necessary. However, this is only
> done at boot time and so waiting here will only have a small impact on boot
> time. Therefore, update tegra_powergate_set() to wait when setting the
> powergate.
>
> By adding this feature, we can also eliminate the polling loop from
> tegra30_boot_secondary().
>
> A macro has also been adding for checking the status of the powergate and
"added"
> so update the tegra_powergate_is_powered() to use this macro as well.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> arch/arm/mach-tegra/platsmp.c | 16 +++-------------
> drivers/soc/tegra/pmc.c | 21 +++++++++++++++------
> 2 files changed, 18 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index b45086666648..40cb761e7c95 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -108,19 +108,9 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
> * be un-gated by un-toggling the power gate register
> * manually.
> */
> - if (!tegra_pmc_cpu_is_powered(cpu)) {
> - ret = tegra_pmc_cpu_power_on(cpu);
> - if (ret)
> - return ret;
> -
> - /* Wait for the power to come up. */
> - timeout = jiffies + msecs_to_jiffies(100);
> - while (!tegra_pmc_cpu_is_powered(cpu)) {
> - if (time_after(jiffies, timeout))
> - return -ETIMEDOUT;
> - udelay(10);
> - }
> - }
> + ret = tegra_pmc_cpu_power_on(cpu);
> + if (ret)
> + return ret;
>
> remove_clamps:
> /* CPU partition is powered. Enable the CPU clock. */
I vaguely remember this being very brittle. I assume you've tested this
extensively and made sure it doesn't regress?
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index fdd1a8d0940f..f94d970089ce 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -28,6 +28,7 @@
> #include <linux/export.h>
> #include <linux/init.h>
> #include <linux/io.h>
> +#include <linux/iopoll.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> #include <linux/platform_device.h>
> @@ -101,6 +102,8 @@
>
> #define GPU_RG_CNTRL 0x2d4
>
> +#define PMC_PWRGATE_STATE(status, id) ((status & BIT(id)) != 0)
> +
This looks suspiciously like a register or register field definition.
Maybe turn this into a static inline function, such as:
static inline bool tegra_powergate_state(u32 status, int id)
{
return (status & BIT(id)) != 0;
}
?
> struct tegra_pmc_soc {
> unsigned int num_powergates;
> const char *const *powergates;
> @@ -181,22 +184,27 @@ static void tegra_pmc_writel(u32 value, unsigned long offset)
> */
> static int tegra_powergate_set(int id, bool new_state)
> {
> - bool status;
> + u32 status;
> + int err = 0;
Initialization to 0 doesn't seem necessary here.
Thierry
[toc] | [next] | [standalone]
| From | Jon Hunter <jonathanh@nvidia.com> |
|---|---|
| Date | 2016-01-15 10:10 +0100 |
| Message-ID | <qR8ym-3Yi-19@gated-at.bofh.it> |
| In reply to | #1309297 |
On 14/01/16 14:01, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Fri, Dec 04, 2015 at 02:57:07PM +0000, Jon Hunter wrote:
>> Currently, the function tegra_powergate_set() simply sets the desired
>> powergate state but does not wait for the state to change. In most cases
>> we should wait for the state to change before proceeding. Currently, there
>> is a case for tegra114 and tegra124 devices where we do not wait when
>> starting the secondary CPU as this is not necessary. However, this is only
>> done at boot time and so waiting here will only have a small impact on boot
>> time. Therefore, update tegra_powergate_set() to wait when setting the
>> powergate.
>>
>> By adding this feature, we can also eliminate the polling loop from
>> tegra30_boot_secondary().
>>
>> A macro has also been adding for checking the status of the powergate and
>
> "added"
Ok, thanks.
>> so update the tegra_powergate_is_powered() to use this macro as well.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>> arch/arm/mach-tegra/platsmp.c | 16 +++-------------
>> drivers/soc/tegra/pmc.c | 21 +++++++++++++++------
>> 2 files changed, 18 insertions(+), 19 deletions(-)
>>
>> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
>> index b45086666648..40cb761e7c95 100644
>> --- a/arch/arm/mach-tegra/platsmp.c
>> +++ b/arch/arm/mach-tegra/platsmp.c
>> @@ -108,19 +108,9 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
>> * be un-gated by un-toggling the power gate register
>> * manually.
>> */
>> - if (!tegra_pmc_cpu_is_powered(cpu)) {
>> - ret = tegra_pmc_cpu_power_on(cpu);
>> - if (ret)
>> - return ret;
>> -
>> - /* Wait for the power to come up. */
>> - timeout = jiffies + msecs_to_jiffies(100);
>> - while (!tegra_pmc_cpu_is_powered(cpu)) {
>> - if (time_after(jiffies, timeout))
>> - return -ETIMEDOUT;
>> - udelay(10);
>> - }
>> - }
>> + ret = tegra_pmc_cpu_power_on(cpu);
>> + if (ret)
>> + return ret;
>>
>> remove_clamps:
>> /* CPU partition is powered. Enable the CPU clock. */
>
> I vaguely remember this being very brittle. I assume you've tested this
> extensively and made sure it doesn't regress?
I have boot tested several times, but if you are concerned about this
secondary boot failing specifically, I could setup a test over the
weekend to boot test say 1000 iterations for all boards.
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index fdd1a8d0940f..f94d970089ce 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -28,6 +28,7 @@
>> #include <linux/export.h>
>> #include <linux/init.h>
>> #include <linux/io.h>
>> +#include <linux/iopoll.h>
>> #include <linux/of.h>
>> #include <linux/of_address.h>
>> #include <linux/platform_device.h>
>> @@ -101,6 +102,8 @@
>>
>> #define GPU_RG_CNTRL 0x2d4
>>
>> +#define PMC_PWRGATE_STATE(status, id) ((status & BIT(id)) != 0)
>> +
>
> This looks suspiciously like a register or register field definition.
> Maybe turn this into a static inline function, such as:
>
> static inline bool tegra_powergate_state(u32 status, int id)
> {
> return (status & BIT(id)) != 0;
> }
>
> ?
Ok.
>> struct tegra_pmc_soc {
>> unsigned int num_powergates;
>> const char *const *powergates;
>> @@ -181,22 +184,27 @@ static void tegra_pmc_writel(u32 value, unsigned long offset)
>> */
>> static int tegra_powergate_set(int id, bool new_state)
>> {
>> - bool status;
>> + u32 status;
>> + int err = 0;
>
> Initialization to 0 doesn't seem necessary here.
Yes, ok.
Cheers
Jon
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web