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| Started by | "Michael S. Tsirkin" <mst@redhat.com> |
|---|---|
| First post | 2016-01-13 21:20 +0100 |
| Last post | 2016-01-13 21:20 +0100 |
| Articles | 1 — 1 participant |
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[PATCH v3 2/4] x86: drop a comment left over from X86_OOSTORE "Michael S. Tsirkin" <mst@redhat.com> - 2016-01-13 21:20 +0100
| From | "Michael S. Tsirkin" <mst@redhat.com> |
|---|---|
| Date | 2016-01-13 21:20 +0100 |
| Subject | [PATCH v3 2/4] x86: drop a comment left over from X86_OOSTORE |
| Message-ID | <qQA3D-4La-1@gated-at.bofh.it> |
The comment about wmb being non-nop to deal with non-intel CPUs is a
left over from before commit 09df7c4c8097 ("x86: Remove
CONFIG_X86_OOSTORE").
It makes no sense now: in particular, wmb is not a nop even for regular
intel CPUs because of weird use-cases e.g. dealing with WC memory.
Drop this comment.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
arch/x86/include/asm/barrier.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index a65bdb1..a291745 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -11,10 +11,6 @@
*/
#ifdef CONFIG_X86_32
-/*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
- * nop for these.
- */
#define mb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "mfence", \
X86_FEATURE_XMM2) ::: "memory", "cc")
#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "lfence", \
--
MST
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