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[PATCH 0/2] DRA72/DRA74: Add 2 lane support

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  [PATCH 0/2] DRA72/DRA74: Add 2 lane support Kishon Vijay Abraham I <kishon@ti.com> - 2016-01-06 12:00 +0100
    [PATCH 1/2] pci: host: pci-dra7xx: use "num-lanes" property to find phy count Kishon Vijay Abraham I <kishon@ti.com> - 2016-01-06 12:00 +0100
    Re: [PATCH 0/2] DRA72/DRA74: Add 2 lane support Bjorn Helgaas <helgaas@kernel.org> - 2016-01-07 18:50 +0100
      Re: [PATCH 0/2] DRA72/DRA74: Add 2 lane support Tony Lindgren <tony@atomide.com> - 2016-01-07 19:20 +0100
        Re: [PATCH 0/2] DRA72/DRA74: Add 2 lane support Kishon Vijay Abraham I <kishon@ti.com> - 2016-01-11 09:10 +0100

#1302625 — [PATCH 0/2] DRA72/DRA74: Add 2 lane support

Add driver modifications in pci-dra7xx to get x2 mode working in
DRA72 and DRA74. Certain modifications is needed in PHY driver also
which will be sent as a separate series.

Certain board modifications has to be done in order to test
x2 mode in dra72-evm.

These patches were created on pci next.

Changes from RFC:
*) .b1co_mode_sel_mask is now set with the correct value.
*) cleanup the patch

Kishon Vijay Abraham I (2):
  pci: host: pci-dra7xx: use "num-lanes" property to find phy count
  pci: host: pci-dra7xx: Enable x2 mode support

 Documentation/devicetree/bindings/pci/ti-pci.txt |    8 +-
 drivers/pci/host/pci-dra7xx.c                    |  104 +++++++++++++++++++---
 2 files changed, 97 insertions(+), 15 deletions(-)

-- 
1.7.9.5

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#1302628 — [PATCH 1/2] pci: host: pci-dra7xx: use "num-lanes" property to find phy count

use "num-lanes" property to find phy count instead of the number
phy-names property.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/pci/host/pci-dra7xx.c |   23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 5963adc..05bbeee 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -70,7 +70,7 @@
 struct dra7xx_pcie {
 	void __iomem		*base;
 	struct phy		**phy;
-	int			phy_count;
+	int			lanes;
 	struct device		*dev;
 	struct pcie_port	pp;
 };
@@ -364,7 +364,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	int ret;
 	int irq;
 	int i;
-	int phy_count;
+	u32 lanes;
 	struct phy **phy;
 	void __iomem *base;
 	struct resource *res;
@@ -402,17 +402,16 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	if (!base)
 		return -ENOMEM;
 
-	phy_count = of_property_count_strings(np, "phy-names");
-	if (phy_count < 0) {
-		dev_err(dev, "unable to find the strings\n");
-		return phy_count;
+	if (of_property_read_u32(np, "num-lanes", &lanes)) {
+		dev_err(dev, "Failed to parse the number of lanes\n");
+		return -EINVAL;
 	}
 
-	phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
+	phy = devm_kzalloc(dev, sizeof(*phy) * lanes, GFP_KERNEL);
 	if (!phy)
 		return -ENOMEM;
 
-	for (i = 0; i < phy_count; i++) {
+	for (i = 0; i < lanes; i++) {
 		snprintf(name, sizeof(name), "pcie-phy%d", i);
 		phy[i] = devm_phy_get(dev, name);
 		if (IS_ERR(phy[i]))
@@ -432,7 +431,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	dra7xx->base = base;
 	dra7xx->phy = phy;
 	dra7xx->dev = dev;
-	dra7xx->phy_count = phy_count;
+	dra7xx->lanes = lanes;
 
 	pm_runtime_enable(dev);
 	ret = pm_runtime_get_sync(dev);
@@ -489,7 +488,7 @@ static int __exit dra7xx_pcie_remove(struct platform_device *pdev)
 	struct dra7xx_pcie *dra7xx = platform_get_drvdata(pdev);
 	struct pcie_port *pp = &dra7xx->pp;
 	struct device *dev = &pdev->dev;
-	int count = dra7xx->phy_count;
+	int count = dra7xx->lanes;
 
 	if (pp->irq_domain)
 		irq_domain_remove(pp->irq_domain);
@@ -535,7 +534,7 @@ static int dra7xx_pcie_resume(struct device *dev)
 static int dra7xx_pcie_suspend_noirq(struct device *dev)
 {
 	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
-	int count = dra7xx->phy_count;
+	int count = dra7xx->lanes;
 
 	while (count--) {
 		phy_power_off(dra7xx->phy[count]);
@@ -548,7 +547,7 @@ static int dra7xx_pcie_suspend_noirq(struct device *dev)
 static int dra7xx_pcie_resume_noirq(struct device *dev)
 {
 	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
-	int phy_count = dra7xx->phy_count;
+	int phy_count = dra7xx->lanes;
 	int ret;
 	int i;
 
-- 
1.7.9.5

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#1303765

[+cc Richard]

Hi Kishon,

On Wed, Jan 06, 2016 at 04:19:51PM +0530, Kishon Vijay Abraham I wrote:
> Add driver modifications in pci-dra7xx to get x2 mode working in
> DRA72 and DRA74. Certain modifications is needed in PHY driver also
> which will be sent as a separate series.
> 
> Certain board modifications has to be done in order to test
> x2 mode in dra72-evm.
> 
> These patches were created on pci next.
> 
> Changes from RFC:
> *) .b1co_mode_sel_mask is now set with the correct value.
> *) cleanup the patch
> 
> Kishon Vijay Abraham I (2):
>   pci: host: pci-dra7xx: use "num-lanes" property to find phy count
>   pci: host: pci-dra7xx: Enable x2 mode support
> 
>  Documentation/devicetree/bindings/pci/ti-pci.txt |    8 +-
>  drivers/pci/host/pci-dra7xx.c                    |  104 +++++++++++++++++++---
>  2 files changed, 97 insertions(+), 15 deletions(-)

Apparently dra7xx in mainline doesn't work [1].  Until that's
resolved, I'm going to ignore dra7xx patches.

Bjorn

[1] http://lkml.kernel.org/r/20160106214518.GA6106@localhost.localdomain

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#1303778

* Bjorn Helgaas <helgaas@kernel.org> [160107 09:42]:
> [+cc Richard]
> 
> Hi Kishon,
> 
> On Wed, Jan 06, 2016 at 04:19:51PM +0530, Kishon Vijay Abraham I wrote:
> > Add driver modifications in pci-dra7xx to get x2 mode working in
> > DRA72 and DRA74. Certain modifications is needed in PHY driver also
> > which will be sent as a separate series.
> > 
> > Certain board modifications has to be done in order to test
> > x2 mode in dra72-evm.
> > 
> > These patches were created on pci next.
> > 
> > Changes from RFC:
> > *) .b1co_mode_sel_mask is now set with the correct value.
> > *) cleanup the patch
> > 
> > Kishon Vijay Abraham I (2):
> >   pci: host: pci-dra7xx: use "num-lanes" property to find phy count
> >   pci: host: pci-dra7xx: Enable x2 mode support
> > 
> >  Documentation/devicetree/bindings/pci/ti-pci.txt |    8 +-
> >  drivers/pci/host/pci-dra7xx.c                    |  104 +++++++++++++++++++---
> >  2 files changed, 97 insertions(+), 15 deletions(-)
> 
> Apparently dra7xx in mainline doesn't work [1].  Until that's
> resolved, I'm going to ignore dra7xx patches.

Agreed. Guys, please do the development _and_ testing on the mainline
kernel. We do have the mainline kernel usable for probably a few
tens of omap SoC variants. If you have issues using dra7 with mainline,
please fix those issues ASAP.

Ideally of course please also use the device you're working on to
send out the patches :)

Regards,

Tony

> [1] http://lkml.kernel.org/r/20160106214518.GA6106@localhost.localdomain

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#1305930

Hi Tony,

On Thursday 07 January 2016 11:43 PM, Tony Lindgren wrote:
> * Bjorn Helgaas <helgaas@kernel.org> [160107 09:42]:
>> [+cc Richard]
>>
>> Hi Kishon,
>>
>> On Wed, Jan 06, 2016 at 04:19:51PM +0530, Kishon Vijay Abraham I wrote:
>>> Add driver modifications in pci-dra7xx to get x2 mode working in
>>> DRA72 and DRA74. Certain modifications is needed in PHY driver also
>>> which will be sent as a separate series.
>>>
>>> Certain board modifications has to be done in order to test
>>> x2 mode in dra72-evm.
>>>
>>> These patches were created on pci next.
>>>
>>> Changes from RFC:
>>> *) .b1co_mode_sel_mask is now set with the correct value.
>>> *) cleanup the patch
>>>
>>> Kishon Vijay Abraham I (2):
>>>   pci: host: pci-dra7xx: use "num-lanes" property to find phy count
>>>   pci: host: pci-dra7xx: Enable x2 mode support
>>>
>>>  Documentation/devicetree/bindings/pci/ti-pci.txt |    8 +-
>>>  drivers/pci/host/pci-dra7xx.c                    |  104 +++++++++++++++++++---
>>>  2 files changed, 97 insertions(+), 15 deletions(-)
>>
>> Apparently dra7xx in mainline doesn't work [1].  Until that's
>> resolved, I'm going to ignore dra7xx patches.
> 
> Agreed. Guys, please do the development _and_ testing on the mainline
> kernel. We do have the mainline kernel usable for probably a few
> tens of omap SoC variants. If you have issues using dra7 with mainline,
> please fix those issues ASAP.

Here Bjorn meant pci-dra7xx is broken in mainline and not the dra7xx boot
as such. (which is due to the absence of reset controller driver).
All the patches to pci-dra7xx were tested on mainline kernel (having
out-of-tree reset patches since the reset controller driver is not merged).
> 
> Ideally of course please also use the device you're working on to
> send out the patches :)

dra7x is the only device that use this pci driver and all the patches to
pci-dra7xx have been tested on both dra7 and dra72 boards.

Thanks
Kishon

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