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Re: [PATCH 2/2] regmap: irq: add support to have callback pre/post irq handling

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  Re: [PATCH 2/2] regmap: irq: add support to have callback pre/post  irq handling Mark Brown <broonie@kernel.org> - 2016-01-05 18:50 +0100
    Re: [PATCH 2/2] regmap: irq: add support to have callback pre/post  irq handling Laxman Dewangan <ldewangan@nvidia.com> - 2016-01-06 07:20 +0100

#1301747 — Re: [PATCH 2/2] regmap: irq: add support to have callback pre/post irq handling

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On Tue, Dec 22, 2015 at 06:25:27PM +0530, Laxman Dewangan wrote:
> Some of devices like MAXIM MAX77620 required to have the chip
> specific configuration before processing interrupt and after
> interrupt handling is done.

I'd like to see the user for this...

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#1302408

Resending as previous response was denied by linux-kernel due to html 
format.

On Tuesday 05 January 2016 11:13 PM, Mark Brown wrote:
> * PGP Signed by an unknown key
>
> On Tue, Dec 22, 2015 at 06:25:27PM +0530, Laxman Dewangan wrote:
>> Some of devices like MAXIM MAX77620 required to have the chip
>> specific configuration before processing interrupt and after
>> interrupt handling is done.
> I'd like to see the user for this...
>

This will be there in my next coming patches for PMIC driver from Maxim 
Semiconductor MAX77620/MAX20024.

Per datasheet:

Upon the interrupt hardware line going low (nIRQ=0), the software is 
switched to the priority decoder which decides in what order all 
interrupts to the processor are serviced and therefore, will transfer 
control to the PMIC interrupt service routine appropriately.

* The first task for the processor is to mask the PMIC interrupt by 
setting GLBLM.
     o This forces nIRQ to go high-impedance in which case it will be 
pulled high by the external pull-up resistor.
     o Forcing nRIQ to go high-impedance ensures that any interrupts 
that occur within the PMIC while the PMIC interrupt service routine is 
being executed will cause a subsequent falling edge on the processor 
interrupt line.

* The next task is to read the IRQTOP register and maintain a local 
copy. Note that IRQTOP is cleared when read.
    // Handle all interrupts which occurred from PMIC.

* Once all interrupts have been checked and serviced, the interrupt 
service routine un-masks the hardware interrupt line by clearing (GLBLM).


And typical code will be:

int max77620_top_irq_chip_pre_irq(void *data)
{
         struct max77620_chip *chip = data;

         ret = max77620_reg_update(chip->dev, MAX77620_PWR_SLAVE,
                 MAX77620_REG_INTENLBT, MAX77620_GLBLM_MASK,
                 MAX77620_GLBLM_MASK);
         ::::
}

int max77620_top_irq_chip_post_irq(void *data)
{
         struct max77620_chip *chip = data;

         ret = max77620_reg_update(chip->dev, MAX77620_PWR_SLAVE,
                 MAX77620_REG_INTENLBT, MAX77620_GLBLM_MASK, 0);
         ::::
}

static struct regmap_irq_chip max77620_top_irq_chip = {
         .pre_irq = max77620_top_irq_chip_pre_irq,
         .post_irq = max77620_top_irq_chip_post_irq,
};
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