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[PATCH 00/24] crypto: atmel-aes: global rework of the driver

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  [PATCH 00/24] crypto: atmel-aes: global rework of the driver Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 17:50 +0100
    [PATCH 02/24] crypto: atmel-aes: constify value argument of atmel_aes_write_n() Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 17:50 +0100
    [PATCH 01/24] crypto: atmel-aes: add new version Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 17:50 +0100
    [PATCH 06/24] crypto: atmel-aes: propagate error from atmel_aes_hw_version_init() Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 11/24] crypto: atmel-aes: rework crypto request completion Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 08/24] crypto: atmel-aes: make crypto request queue management more generic Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 14/24] crypto: atmel-aes: remove useless AES_FLAGS_DMA flag Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 15/24] crypto: atmel-aes: fix atmel_aes_remove() Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 10/24] crypto: atmel-aes: simplify the configuration of the AES IP Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 13/24] crypto: atmel-aes: reduce latency of DMA completion Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 07/24] crypto: atmel-aes: change atmel_aes_write_ctrl() signature Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 12/24] crypto: atmel-aes: remove unused 'err' member of struct atmel_aes_dev Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 09/24] crypto: atmel-aes: remove useless write in the Control Register Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:00 +0100
    [PATCH 18/24] crypto: atmel-aes: fix typo and indentation Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 22/24] crypto: atmel-aes: change the DMA threshold Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 20/24] crypto: atmel-aes: fix atmel-ctr-aes driver for RFC 3686 Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 23/24] crypto: atmel-aes: add support to GCM mode Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 16/24] crypto: atmel-aes: improve performances of data transfer Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 24/24] crypto: atmel-aes: add debug facilities to monitor register accesses. Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 19/24] crypto: atmel-aes: create sections to regroup functions by usage Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 21/24] crypto: atmel-aes: fix the counter overflow in CTR mode Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    [PATCH 17/24] crypto: atmel-aes: use SIZE_IN_WORDS() helper macro Cyrille Pitchen <cyrille.pitchen@atmel.com> - 2015-12-17 18:20 +0100
    Re: [PATCH 00/24] crypto: atmel-aes: global rework of the driver Herbert Xu <herbert@gondor.apana.org.au> - 2015-12-23 11:30 +0100

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#1294071 — [PATCH 21/24] crypto: atmel-aes: fix the counter overflow in CTR mode

Depending on its hardware version, the AES IP provides either a 16 or a
32 bit counter. However the CTR mode expects the size of the counter to be
the same as the size of the cipher block, ie 128 bits for AES.
This patch detects and handles counter overflows.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
 drivers/crypto/atmel-aes.c | 117 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 115 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c
index 5f6dc48616c0..a34919f6b7d7 100644
--- a/drivers/crypto/atmel-aes.c
+++ b/drivers/crypto/atmel-aes.c
@@ -82,6 +82,7 @@
 struct atmel_aes_caps {
 	bool			has_dualbuff;
 	bool			has_cfb64;
+	bool			has_ctr32;
 	u32			max_burst_size;
 };
 
@@ -103,6 +104,15 @@ struct atmel_aes_ctx {
 	struct atmel_aes_base_ctx	base;
 };
 
+struct atmel_aes_ctr_ctx {
+	struct atmel_aes_base_ctx	base;
+
+	u32			iv[AES_BLOCK_SIZE / sizeof(u32)];
+	size_t			offset;
+	struct scatterlist	src[2];
+	struct scatterlist	dst[2];
+};
+
 struct atmel_aes_reqctx {
 	unsigned long		mode;
 };
@@ -762,6 +772,96 @@ static int atmel_aes_start(struct atmel_aes_dev *dd)
 				   atmel_aes_transfer_complete);
 }
 
+static inline struct atmel_aes_ctr_ctx *
+atmel_aes_ctr_ctx_cast(struct atmel_aes_base_ctx *ctx)
+{
+	return container_of(ctx, struct atmel_aes_ctr_ctx, base);
+}
+
+static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd)
+{
+	struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
+	struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
+	struct scatterlist *src, *dst;
+	u32 ctr, blocks;
+	size_t datalen;
+	bool use_dma, fragmented = false;
+
+	/* Check for transfer completion. */
+	ctx->offset += dd->total;
+	if (ctx->offset >= req->nbytes)
+		return atmel_aes_transfer_complete(dd);
+
+	/* Compute data length. */
+	datalen = req->nbytes - ctx->offset;
+	blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);
+	ctr = be32_to_cpu(ctx->iv[3]);
+	if (dd->caps.has_ctr32) {
+		/* Check 32bit counter overflow. */
+		u32 start = ctr;
+		u32 end = start + blocks - 1;
+
+		if (end < start) {
+			ctr |= 0xffffffff;
+			datalen = AES_BLOCK_SIZE * -start;
+			fragmented = true;
+		}
+	} else {
+		/* Check 16bit counter overflow. */
+		u16 start = ctr & 0xffff;
+		u16 end = start + (u16)blocks - 1;
+
+		if (blocks >> 16 || end < start) {
+			ctr |= 0xffff;
+			datalen = AES_BLOCK_SIZE * (0x10000-start);
+			fragmented = true;
+		}
+	}
+	use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);
+
+	/* Jump to offset. */
+	src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset);
+	dst = ((req->src == req->dst) ? src :
+	       scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset));
+
+	/* Configure hardware. */
+	atmel_aes_write_ctrl(dd, use_dma, ctx->iv);
+	if (unlikely(fragmented)) {
+		/*
+		 * Increment the counter manually to cope with the hardware
+		 * counter overflow.
+		 */
+		ctx->iv[3] = cpu_to_be32(ctr);
+		crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE);
+	}
+
+	if (use_dma)
+		return atmel_aes_dma_start(dd, src, dst, datalen,
+					   atmel_aes_ctr_transfer);
+
+	return atmel_aes_cpu_start(dd, src, dst, datalen,
+				   atmel_aes_ctr_transfer);
+}
+
+static int atmel_aes_ctr_start(struct atmel_aes_dev *dd)
+{
+	struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);
+	struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
+	struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
+	int err;
+
+	atmel_aes_set_mode(dd, rctx);
+
+	err = atmel_aes_hw_init(dd);
+	if (err)
+		return atmel_aes_complete(dd, err);
+
+	memcpy(ctx->iv, req->info, AES_BLOCK_SIZE);
+	ctx->offset = 0;
+	dd->total = 0;
+	return atmel_aes_ctr_transfer(dd);
+}
+
 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 {
 	struct atmel_aes_base_ctx *ctx;
@@ -919,6 +1019,16 @@ static int atmel_aes_cra_init(struct crypto_tfm *tfm)
 	return 0;
 }
 
+static int atmel_aes_ctr_cra_init(struct crypto_tfm *tfm)
+{
+	struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+
+	tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
+	ctx->base.start = atmel_aes_ctr_start;
+
+	return 0;
+}
+
 static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
 {
 }
@@ -1076,11 +1186,11 @@ static struct crypto_alg aes_algs[] = {
 	.cra_priority		= ATMEL_AES_PRIORITY,
 	.cra_flags		= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
 	.cra_blocksize		= 1,
-	.cra_ctxsize		= sizeof(struct atmel_aes_ctx),
+	.cra_ctxsize		= sizeof(struct atmel_aes_ctr_ctx),
 	.cra_alignmask		= 0xf,
 	.cra_type		= &crypto_ablkcipher_type,
 	.cra_module		= THIS_MODULE,
-	.cra_init		= atmel_aes_cra_init,
+	.cra_init		= atmel_aes_ctr_cra_init,
 	.cra_exit		= atmel_aes_cra_exit,
 	.cra_u.ablkcipher = {
 		.min_keysize	= AES_MIN_KEY_SIZE,
@@ -1262,6 +1372,7 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
 {
 	dd->caps.has_dualbuff = 0;
 	dd->caps.has_cfb64 = 0;
+	dd->caps.has_ctr32 = 0;
 	dd->caps.max_burst_size = 1;
 
 	/* keep only major version number */
@@ -1269,11 +1380,13 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
 	case 0x500:
 		dd->caps.has_dualbuff = 1;
 		dd->caps.has_cfb64 = 1;
+		dd->caps.has_ctr32 = 1;
 		dd->caps.max_burst_size = 4;
 		break;
 	case 0x200:
 		dd->caps.has_dualbuff = 1;
 		dd->caps.has_cfb64 = 1;
+		dd->caps.has_ctr32 = 1;
 		dd->caps.max_burst_size = 4;
 		break;
 	case 0x130:
-- 
1.8.2.2

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#1294073 — [PATCH 17/24] crypto: atmel-aes: use SIZE_IN_WORDS() helper macro

This is a dummy cosmetic patch.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
---
 drivers/crypto/atmel-aes.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c
index 9ef38eca4ae7..176ab3878583 100644
--- a/drivers/crypto/atmel-aes.c
+++ b/drivers/crypto/atmel-aes.c
@@ -689,10 +689,10 @@ static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
 	atmel_aes_write(dd, AES_MR, valmr);
 
 	atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
-						dd->ctx->keylen >> 2);
+			  SIZE_IN_WORDS(dd->ctx->keylen));
 
 	if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
-		atmel_aes_write_n(dd, AES_IVR(0), iv, 4);
+		atmel_aes_write_block(dd, AES_IVR(0), iv);
 }
 
 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
-- 
1.8.2.2

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#1297318

On Thu, Dec 17, 2015 at 05:48:31PM +0100, Cyrille Pitchen wrote:
> Hi all,
> 
> this series of patches is a global rework of the Atmel driver. Some
> patches improve the performances whereas others fix some bugs like
> the counter overflow in CTR mode.
> 
> It also updates some part of the code to make them more generic. For
> instance the crypto request queue management supports both async block
> cipher and AEAD requests, which allows us to add support the the GCM
> mode. The support of the GCM mode is only available on sama5d4 and later.
> 
> This series is based on linux-next and was tested on sama5d2, sama5d3 and
> sama5d4 boards. The driver implementation was validated using the tcrypt
> module running modes:
> - 10: ecb(aes), cbc(aes), ctr(aes), rfc3686(ctr(aes))
> - 35: gcm(aes)
> 
> tcrypt speed test was run with modes:
> - 211: rfc4106(gcm(aes)), gcm(aes)
> - 500: ecb(aes), cbc(aes), ctr(aes), cfb(aes), ofc(aes), rfc3686(ctr(aes))
> 
> Finally iperf was run for at least 5 mins over an IPSEC/L2TP tunnel using
> the rfc4106(gcm(aes)) cipher suite.

All applied.  Thanks!
-- 
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