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Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock

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  Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock Ulf Hansson <ulf.hansson@linaro.org> - 2015-12-16 11:20 +0100
    Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock "Ivan T. Ivanov" <ivan.ivanov@linaro.org> - 2015-12-16 12:50 +0100
      Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock Ulf Hansson <ulf.hansson@linaro.org> - 2015-12-16 14:50 +0100

#1292862 — Re: [PATCH v2] mmc: sdhci-msm: Boost controller core clock

[...]

>> It seems like a reasonable assumption that the controller can't cope
>> with a higher clock rate than 100 MHz as "input" clock. That would
>> then mean that there are different versions of the controller, as it
>> seems like for some version it's fine with 200MHz and for some 100MHz.
>>
>> According to the DT compatible strings, *one* version is currently
>> supported, "qcom,sdhci-msm-v4"...
>
> The same version of hardware is there 4 times. The difference is
> the maximum clock frequency supported by them is different. In
> downstream kernels we've handled this by trimming the frequency
> tables for the different controllers in the clock driver.
> Setting the clock to INT_MAX will make it run at 400MHz, which
> doesn't look to be supported by anything besides sdc1 on 8974ac.
>
>>
>> I see two viable solutions. One would be to limit the clock rate
>> depending on the version of the controller (new compatible strings
>> needs to be added). Another one would be to limit the clock rate by
>> using the existing DT binding for max-frequency, and thus do a
>> clk_set_rate(mmc->f_max) during probe.
>>
>
> I'd rather see that done via OPP tables in DT, but I suppose
> max-frequency is fine too. We'll need to use OPPs soon enough
> because there's a voltage associated with that frequency.
>
> In case you're wondering, the max frequency for sdc1 on 8974ac is
> 400MHz. If it's just a plain 8974pro then the max frequency is
> 200MHz. Otherwise, sdc2 maxes out at 200Mhz and sdc3 and sdc4 max
> out at 100MHz.
>

I think we have reached a consensus on the viable options.

As we haven't heard from Ivan, do someone want to send a patch for
this or shall we just revert $subject patch (which I can deal with)?

Kind regards
Uffe
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#1292917

> On Dec 16, 2015, at 12:18 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> 
> [...]
> 
>>> It seems like a reasonable assumption that the controller can't cope
>>> with a higher clock rate than 100 MHz as "input" clock. That would
>>> then mean that there are different versions of the controller, as it
>>> seems like for some version it's fine with 200MHz and for some 100MHz.
>>> 
>>> According to the DT compatible strings, *one* version is currently
>>> supported, "qcom,sdhci-msm-v4"...
>> 
>> The same version of hardware is there 4 times. The difference is
>> the maximum clock frequency supported by them is different. In
>> downstream kernels we've handled this by trimming the frequency
>> tables for the different controllers in the clock driver.
>> Setting the clock to INT_MAX will make it run at 400MHz, which
>> doesn't look to be supported by anything besides sdc1 on 8974ac.
>> 
>>> 
>>> I see two viable solutions. One would be to limit the clock rate
>>> depending on the version of the controller (new compatible strings
>>> needs to be added). Another one would be to limit the clock rate by
>>> using the existing DT binding for max-frequency, and thus do a
>>> clk_set_rate(mmc->f_max) during probe.
>>> 
>> 
>> I'd rather see that done via OPP tables in DT, but I suppose
>> max-frequency is fine too. We'll need to use OPPs soon enough
>> because there's a voltage associated with that frequency.
>> 
>> In case you're wondering, the max frequency for sdc1 on 8974ac is
>> 400MHz. If it's just a plain 8974pro then the max frequency is
>> 200MHz. Otherwise, sdc2 maxes out at 200Mhz and sdc3 and sdc4 max
>> out at 100MHz.
>> 
> 
> I think we have reached a consensus on the viable options.
> 
> As we haven't heard from Ivan, do someone want to send a patch for
> this or shall we just revert $subject patch (which I can deal with)?

I am following this discussion, but I am not sure what I could do. 

If my understanding is correct, even if controllers report same version,
they don’t support 400MHz core clock. 

Initial patch fixes real issue. I am voting for “max-frequency” DT property.

I don’t have 8974ac, so I can not test the change.

Regards,
Ivan

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#1292963

On 16 December 2015 at 12:44, Ivan T. Ivanov <ivan.ivanov@linaro.org> wrote:
>
>> On Dec 16, 2015, at 12:18 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>>
>> [...]
>>
>>>> It seems like a reasonable assumption that the controller can't cope
>>>> with a higher clock rate than 100 MHz as "input" clock. That would
>>>> then mean that there are different versions of the controller, as it
>>>> seems like for some version it's fine with 200MHz and for some 100MHz.
>>>>
>>>> According to the DT compatible strings, *one* version is currently
>>>> supported, "qcom,sdhci-msm-v4"...
>>>
>>> The same version of hardware is there 4 times. The difference is
>>> the maximum clock frequency supported by them is different. In
>>> downstream kernels we've handled this by trimming the frequency
>>> tables for the different controllers in the clock driver.
>>> Setting the clock to INT_MAX will make it run at 400MHz, which
>>> doesn't look to be supported by anything besides sdc1 on 8974ac.
>>>
>>>>
>>>> I see two viable solutions. One would be to limit the clock rate
>>>> depending on the version of the controller (new compatible strings
>>>> needs to be added). Another one would be to limit the clock rate by
>>>> using the existing DT binding for max-frequency, and thus do a
>>>> clk_set_rate(mmc->f_max) during probe.
>>>>
>>>
>>> I'd rather see that done via OPP tables in DT, but I suppose
>>> max-frequency is fine too. We'll need to use OPPs soon enough
>>> because there's a voltage associated with that frequency.
>>>
>>> In case you're wondering, the max frequency for sdc1 on 8974ac is
>>> 400MHz. If it's just a plain 8974pro then the max frequency is
>>> 200MHz. Otherwise, sdc2 maxes out at 200Mhz and sdc3 and sdc4 max
>>> out at 100MHz.
>>>
>>
>> I think we have reached a consensus on the viable options.
>>
>> As we haven't heard from Ivan, do someone want to send a patch for
>> this or shall we just revert $subject patch (which I can deal with)?
>
> I am following this discussion, but I am not sure what I could do.
>
> If my understanding is correct, even if controllers report same version,
> they don’t support 400MHz core clock.

Correct.

>
> Initial patch fixes real issue. I am voting for “max-frequency” DT property.

I don't have any strong opinion, so I am fine with that approach.

That means at ->probe() we need to consider whether "host->f_max" has
been obtained via DT (mmc_of_parse() parses the "max-frequency" DT
property).
If that's the case, we can choose between two solutions.

1) Consider f_max as the correct value to set via clk_set_rate() and
if f_max isn't available, fall back to a lower "default" frequency to
make sure we are safe.
2) Consider f_max as an upper limit. That means if f_max isn't
available we use INT_MAX instead.

Both alternatives requires DTB to be updated, but option 1) may be
safer as it should allow all cards to be functional, although running
in a lower frequency potentially affecting throughput.

But again, I don't care much, alternative 2 is okay by me as well.

>
> I don’t have 8974ac, so I can not test the change.
>

Let's hope for some help here then!

Kind regards
Uffe
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