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| Started by | Michael Ellerman <mpe@ellerman.id.au> |
|---|---|
| First post | 2015-12-15 12:30 +0100 |
| Last post | 2015-12-15 12:30 +0100 |
| Articles | 1 — 1 participant |
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Re: [powerpc/next, 1/2] powerpc: Make value-returning atomics fully ordered Michael Ellerman <mpe@ellerman.id.au> - 2015-12-15 12:30 +0100
| From | Michael Ellerman <mpe@ellerman.id.au> |
|---|---|
| Date | 2015-12-15 12:30 +0100 |
| Subject | Re: [powerpc/next, 1/2] powerpc: Make value-returning atomics fully ordered |
| Message-ID | <qFVXR-3nl-47@gated-at.bofh.it> |
On Mon, 2015-02-11 at 01:30:31 UTC, Boqun Feng wrote: > According to memory-barriers.txt: > > > Any atomic operation that modifies some state in memory and returns > > information about the state (old or new) implies an SMP-conditional > > general memory barrier (smp_mb()) on each side of the actual > > operation ... > > Which mean these operations should be fully ordered. However on PPC, > PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation, > which is currently "lwsync" if SMP=y. The leading "lwsync" can not > guarantee fully ordered atomics, according to Paul Mckenney: > > https://lkml.org/lkml/2015/10/14/970 > > To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee > the fully-ordered semantics. > > This also makes futex atomics fully ordered, which can avoid possible > memory ordering problems if userspace code relies on futex system call > for fully ordered semantics. > > Cc: <stable@vger.kernel.org> # 3.4+ > Signed-off-by: Boqun Feng <boqun.feng@gmail.com> > Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> > Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/49e9cf3f0c04bf76ffa59242 cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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