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| Started by | Michael Ellerman <mpe@ellerman.id.au> |
|---|---|
| First post | 2015-12-15 12:30 +0100 |
| Last post | 2015-12-15 12:30 +0100 |
| Articles | 1 — 1 participant |
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Re: [powerpc/next, 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered Michael Ellerman <mpe@ellerman.id.au> - 2015-12-15 12:30 +0100
| From | Michael Ellerman <mpe@ellerman.id.au> |
|---|---|
| Date | 2015-12-15 12:30 +0100 |
| Subject | Re: [powerpc/next, 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered |
| Message-ID | <qFVXQ-3nl-31@gated-at.bofh.it> |
On Mon, 2015-02-11 at 01:30:32 UTC, Boqun Feng wrote:
> According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
> versions all need to be fully ordered, however they are now just
> RELEASE+ACQUIRE, which are not fully ordered.
>
> So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
> PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
> __{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
> of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
> b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
>
> This patch depends on patch "powerpc: Make value-returning atomics fully
> ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
>
> Cc: <stable@vger.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
> Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/81d7a3294de7e9828310bbf9
cheers
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