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[PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region

Started byVignesh R <vigneshr@ti.com>
First post2015-12-11 05:20 +0100
Last post2015-12-18 17:50 +0100
Articles 5 — 3 participants

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  [PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region Vignesh R <vigneshr@ti.com> - 2015-12-11 05:20 +0100
    Re: [PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region Rob Herring <robh@kernel.org> - 2015-12-11 16:10 +0100
      Re: [PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region Tony Lindgren <tony@atomide.com> - 2015-12-17 19:50 +0100
        Re: [PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region Vignesh R <vigneshr@ti.com> - 2015-12-18 07:00 +0100
          Re: [PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region Tony Lindgren <tony@atomide.com> - 2015-12-18 17:50 +0100

#1289125 — [PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region

FromVignesh R <vigneshr@ti.com>
Date2015-12-11 05:20 +0100
Subject[PATCH v5 4/5] ARM: dts: DRA7: add entry for qspi mmap region
Message-ID<qEnlv-7xm-1@gated-at.bofh.it>
Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
update the binding documents for the controller to document this change.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---

v5: use syscon to access scm register.

 Documentation/devicetree/bindings/spi/ti_qspi.txt | 17 +++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi                       |  6 ++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 601a360531a5..809c3f334316 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -15,6 +15,10 @@ Recommended properties:
 - spi-max-frequency: Definition as per
                      Documentation/devicetree/bindings/spi/spi-bus.txt
 
+Optional properties:
+- syscon-chipselects: Handle to system control region contains QSPI
+		      chipselect register and offset of that register.
+
 Example:
 
 qspi: qspi@4b300000 {
@@ -26,3 +30,16 @@ qspi: qspi@4b300000 {
 	spi-max-frequency = <25000000>;
 	ti,hwmods = "qspi";
 };
+
+For dra7xx:
+qspi: qspi@4b300000 {
+	compatible = "ti,dra7xxx-qspi";
+	reg = <0x4b300000 0x100>,
+	      <0x5c000000 0x4000000>,
+	reg-names = "qspi_base", "qspi_mmap";
+	syscon-chipselects = <&scm_conf 0x558>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	spi-max-frequency = <48000000>;
+	ti,hwmods = "qspi";
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index fe99231cbde5..be91c7781c07 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1153,8 +1153,10 @@
 
 		qspi: qspi@4b300000 {
 			compatible = "ti,dra7xxx-qspi";
-			reg = <0x4b300000 0x100>;
-			reg-names = "qspi_base";
+			reg = <0x4b300000 0x100>,
+			      <0x5c000000 0x4000000>;
+			reg-names = "qspi_base", "qspi_mmap";
+			syscon-chipselects = <&scm_conf 0x558>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "qspi";
-- 
2.6.3

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#1289658

FromRob Herring <robh@kernel.org>
Date2015-12-11 16:10 +0100
Message-ID<qExuy-69x-15@gated-at.bofh.it>
In reply to#1289125
On Fri, Dec 11, 2015 at 09:39:59AM +0530, Vignesh R wrote:
> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> update the binding documents for the controller to document this change.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Acked-by: Rob Herring <robh@kernel.org>

> ---
> 
> v5: use syscon to access scm register.
> 
>  Documentation/devicetree/bindings/spi/ti_qspi.txt | 17 +++++++++++++++++
>  arch/arm/boot/dts/dra7.dtsi                       |  6 ++++--
>  2 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
> index 601a360531a5..809c3f334316 100644
> --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
> +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
> @@ -15,6 +15,10 @@ Recommended properties:
>  - spi-max-frequency: Definition as per
>                       Documentation/devicetree/bindings/spi/spi-bus.txt
>  
> +Optional properties:
> +- syscon-chipselects: Handle to system control region contains QSPI
> +		      chipselect register and offset of that register.
> +
>  Example:
>  
>  qspi: qspi@4b300000 {
> @@ -26,3 +30,16 @@ qspi: qspi@4b300000 {
>  	spi-max-frequency = <25000000>;
>  	ti,hwmods = "qspi";
>  };
> +
> +For dra7xx:
> +qspi: qspi@4b300000 {
> +	compatible = "ti,dra7xxx-qspi";
> +	reg = <0x4b300000 0x100>,
> +	      <0x5c000000 0x4000000>,
> +	reg-names = "qspi_base", "qspi_mmap";
> +	syscon-chipselects = <&scm_conf 0x558>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	spi-max-frequency = <48000000>;
> +	ti,hwmods = "qspi";
> +};
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index fe99231cbde5..be91c7781c07 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -1153,8 +1153,10 @@
>  
>  		qspi: qspi@4b300000 {
>  			compatible = "ti,dra7xxx-qspi";
> -			reg = <0x4b300000 0x100>;
> -			reg-names = "qspi_base";
> +			reg = <0x4b300000 0x100>,
> +			      <0x5c000000 0x4000000>;
> +			reg-names = "qspi_base", "qspi_mmap";
> +			syscon-chipselects = <&scm_conf 0x558>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "qspi";
> -- 
> 2.6.3
> 
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#1294134

FromTony Lindgren <tony@atomide.com>
Date2015-12-17 19:50 +0100
Message-ID<qGLMK-3bD-9@gated-at.bofh.it>
In reply to#1289658
* Rob Herring <robh@kernel.org> [151211 07:10]:
> On Fri, Dec 11, 2015 at 09:39:59AM +0530, Vignesh R wrote:
> > Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> > update the binding documents for the controller to document this change.
> > 
> > Signed-off-by: Vignesh R <vigneshr@ti.com>
> 
> Acked-by: Rob Herring <robh@kernel.org>

Vignes, are patches 4 and 5 safe to apply separately already or
do things break if we do that?

Regards,

Tony
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#1294447

FromVignesh R <vigneshr@ti.com>
Date2015-12-18 07:00 +0100
Message-ID<qGWf8-1xA-7@gated-at.bofh.it>
In reply to#1294134

On 12/18/2015 12:15 AM, Tony Lindgren wrote:
> * Rob Herring <robh@kernel.org> [151211 07:10]:
>> On Fri, Dec 11, 2015 at 09:39:59AM +0530, Vignesh R wrote:
>>> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
>>> update the binding documents for the controller to document this change.
>>>
>>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>>
>> Acked-by: Rob Herring <robh@kernel.org>
> 
> Vignes, are patches 4 and 5 safe to apply separately already or
> do things break if we do that?

Yes, 4 and 5 can be applied separately w/o driver changes.

-- 
Regards
Vignesh
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#1295025

FromTony Lindgren <tony@atomide.com>
Date2015-12-18 17:50 +0100
Message-ID<qH6o9-86R-7@gated-at.bofh.it>
In reply to#1294447
* Vignesh R <vigneshr@ti.com> [151217 21:51]:
> 
> 
> On 12/18/2015 12:15 AM, Tony Lindgren wrote:
> > * Rob Herring <robh@kernel.org> [151211 07:10]:
> >> On Fri, Dec 11, 2015 at 09:39:59AM +0530, Vignesh R wrote:
> >>> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> >>> update the binding documents for the controller to document this change.
> >>>
> >>> Signed-off-by: Vignesh R <vigneshr@ti.com>
> >>
> >> Acked-by: Rob Herring <robh@kernel.org>
> > 
> > Vignes, are patches 4 and 5 safe to apply separately already or
> > do things break if we do that?
> 
> Yes, 4 and 5 can be applied separately w/o driver changes.

OK picking 4 and 5 into omap-for-v4.5/dt thanks.

Tony
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