Groups > linux.kernel > #1285836 > unrolled thread

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

Started by	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
First post	2015-12-07 19:20 +0100
Last post	2015-12-09 14:20 +0100
Articles	5 on this page of 25 — 5 participants

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  [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for  Exynos542x/5800 platforms Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:20 +0100
    [PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply  properties Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:20 +0100
      Re: [PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator  supply properties Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-08 07:50 +0100
      Re: [PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator  supply properties Markus Reichl <m.reichl@fivetechno.de> - 2015-12-08 11:20 +0100
    [PATCH v4 2/8] clk: samsung: exynos5420: add cpu clock configuration  data and instantiate cpu clock Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:20 +0100
    [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:30 +0100
      Re: [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties Viresh Kumar <viresh.kumar@linaro.org> - 2015-12-08 07:30 +0100
      Re: [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-08 08:20 +0100
    [PATCH v4 8/8] ARM: Exynos: use generic cpufreq driver for  Exynos5422/5800 Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:30 +0100
    [PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:30 +0100
      Re: [PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-08 09:10 +0100
    [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:30 +0100
      Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-08 09:20 +0100
        Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Javier Martinez Canillas <javier@osg.samsung.com> - 2015-12-08 14:50 +0100
          Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-09 01:40 +0100
            Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Javier Martinez Canillas <javier@osg.samsung.com> - 2015-12-09 03:20 +0100
        Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-10 17:00 +0100
    [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420 Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:30 +0100
      Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for  Exynos5420 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-08 08:40 +0100
        Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for  Exynos5420 Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-10 15:20 +0100
          Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for  Exynos5420 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-11 02:20 +0100
    [PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock  configuration data Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2015-12-07 19:30 +0100
    Re: [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for  Exynos542x/5800 platforms Viresh Kumar <viresh.kumar@linaro.org> - 2015-12-08 07:20 +0100
      Re: [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for  Exynos542x/5800 platforms Viresh Kumar <viresh.kumar@linaro.org> - 2015-12-08 07:30 +0100
    Re: [PATCH v4 0/8] cpufreq: add generic cpufreq driver support for  Exynos542x/5800 platforms Javier Martinez Canillas <javier@osg.samsung.com> - 2015-12-09 14:20 +0100

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#1289039 — Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

From	Krzysztof Kozlowski <k.kozlowski@samsung.com>
Date	2015-12-11 02:20 +0100
Subject	Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420
Message-ID	<qEkxk-5EV-9@gated-at.bofh.it>
In reply to	#1288524

On 10.12.2015 23:18, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> On Tuesday, December 08, 2015 04:36:12 PM Krzysztof Kozlowski wrote:
>> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
>>> From: Thomas Abraham <thomas.ab@samsung.com>
>>>
>>> The new CPU clock type allows the use of cpufreq-dt driver
>>> for Exynos5420.
>>>
>>> Changes by Bartlomiej:
>>> - split Exynos5420 support from the original patch
>>> - disable cpufreq if big.LITTLE switcher support is enabled
>>> - switch to using cpufreq-dt driver
>>>
>>> Cc: Tomasz Figa <tomasz.figa@gmail.com>
>>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>>> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/exynos.c | 3 +++
>>>  1 file changed, 3 insertions(+)
>>
>> I think this is actually now your patch, not Thomas any more. :)
> 
> It seems so, I'll update the patch.
> 
>>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>>> index 1c47aee..7a89c9d 100644
>>> --- a/arch/arm/mach-exynos/exynos.c
>>> +++ b/arch/arm/mach-exynos/exynos.c
>>> @@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
>>>  	{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
>>>  	{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
>>>  	{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
>>> +#ifndef CONFIG_BL_SWITCHER
>>> +	{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
>>> +#endif
>>
>> Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?
> 
> ARM_DT_BL_CPUFREQ is not relevant here (it requires to be explicitly
> enabled by platform code, just like cpufreq-dt) and the dependency on
> !BL_SWITCHER is needed because when BL_SWITCHER is enabled big and
> LITTLE cores are grouped in pairs and presented as "virtual" CPUs to
> the system:
> 
> ...
> [    0.002630] CPU0: update cpu_capacity 448
> [    0.002646] CPU0: thread -1, cpu 0, socket 1, mpidr 80000100
> [    0.002835] Setting up static identity map for 0x40008280 - 0x400082d8
> [    0.003106] ARM CCI driver probed
> [    0.003351] Exynos MCPM support installed
> [    0.045350] CPU1: update cpu_capacity 448
> [    0.045358] CPU1: thread -1, cpu 1, socket 1, mpidr 80000101
> [    0.060326] CPU2: update cpu_capacity 448
> [    0.060334] CPU2: thread -1, cpu 2, socket 1, mpidr 80000102
> [    0.075326] CPU3: update cpu_capacity 448
> [    0.075334] CPU3: thread -1, cpu 3, socket 1, mpidr 80000103
> [    0.090337] CPU4: update cpu_capacity 1535
> [    0.090345] CPU4: thread -1, cpu 0, socket 0, mpidr 80000000
> [    0.105314] CPU5: update cpu_capacity 1535
> [    0.105321] CPU5: thread -1, cpu 1, socket 0, mpidr 80000001
> [    0.120338] CPU6: update cpu_capacity 1535
> [    0.120345] CPU6: thread -1, cpu 2, socket 0, mpidr 80000002
> [    0.135330] CPU7: update cpu_capacity 1535
> [    0.135338] CPU7: thread -1, cpu 3, socket 0, mpidr 80000003
> [    0.135466] Brought up 8 CPUs
> ...
> [    3.027498] big.LITTLE switcher initializing
> [    3.031761] CPU0 paired with CPU7
> [    3.035055] CPU1 paired with CPU6
> [    3.038332] CPU2 paired with CPU5
> [    3.041598] CPU3 paired with CPU4
> [    3.044930] GIC ID for CPU 0 cluster 1 is 4
> [    3.049078] GIC ID for CPU 1 cluster 1 is 5
> [    3.053258] GIC ID for CPU 2 cluster 1 is 6
> [    3.057370] GIC ID for CPU 3 cluster 1 is 7
> [    3.061558] GIC ID for CPU 0 cluster 0 is 0
> [    3.083336] IRQ53 no longer affine to CPU4
> [    3.084336] CPU4: shutdown
> [    3.107059] GIC ID for CPU 1 cluster 0 is 1
> [    3.123303] IRQ54 no longer affine to CPU5
> [    3.124213] CPU5: shutdown
> [    3.146387] GIC ID for CPU 2 cluster 0 is 2
> [    3.158143] cpu cpu0: 1100 MHz, 1250 mV --> 900 MHz, 1100 mV
> [    3.168228] IRQ55 no longer affine to CPU6
> [    3.169135] CPU6: shutdown
> [    3.191485] GIC ID for CPU 3 cluster 0 is 3
> [    3.208264] IRQ56 no longer affine to CPU7
> [    3.209166] CPU7: shutdown
> [    3.236752] big.LITTLE switcher initialized
> ...
> 
> Only arm_big_little_dt driver knows how to handle this setup
> correctly.  cpufreq-dt just treats "virtual" CPUs as a LITTLE
> ones.  Thus when "virtual CPU"'s current core is switched to
> a big one cpufreq-dt is unable to update its voltage.
> 
> [ I tried using BL_SWITCHER_DUMMY_IF functionality to simulate
>   this with:
> 
> 	echo 0,0 > /dev/b.L_switcher
> 
>   but it doesn't seem to work for some reason (from looking at
>   arch/arm/common/bL_switcher_dummy_if.c code it seems that at
>   least "bL_switcher_write" line should get logged but it does
>   not happen). ]

Thank you for explanation, seems good approach.

Best regards,
Krzysztof


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#1285850 — [PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock configuration data

From	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Date	2015-12-07 19:30 +0100
Subject	[PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock configuration data
Message-ID	<qD8HW-8aH-67@gated-at.bofh.it>
In reply to	#1285836

Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
 	{  0 },
 };
 
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+	{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+	{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+	{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+	{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+	{  900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+	{  800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+	{  700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+	{  600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+	{  500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+	{  0 },
+};
+
 #define E5420_KFC_DIV(kpll, pclk, aclk)					\
 		((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
 
 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+	{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
 	{ 1300000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1200000, E5420_KFC_DIV(3, 5, 2), },
 	{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
 				ARRAY_SIZE(exynos5800_gate_clks));
 	}
 
-	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
-		mout_cpu_p[0], mout_cpu_p[1], 0x200,
-		exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	if (soc == EXYNOS5420) {
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+	} else {
+		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+			mout_cpu_p[0], mout_cpu_p[1], 0x200,
+			exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+	}
 	exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
 		mout_kfc_p[0], mout_kfc_p[1], 0x28200,
 		exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
-- 
1.9.1

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#1286260

From	Viresh Kumar <viresh.kumar@linaro.org>
Date	2015-12-08 07:20 +0100
Message-ID	<qDjMZ-733-3@gated-at.bofh.it>
In reply to	#1285836

On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> Hi,
> 
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
> 
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.

Excellent work Bartlomiej. Thanks a lot for adapting cpufreq-dt for
this. Really appreciate it :)

-- 
viresh
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#1286266

From	Viresh Kumar <viresh.kumar@linaro.org>
Date	2015-12-08 07:30 +0100
Message-ID	<qDjWG-76S-11@gated-at.bofh.it>
In reply to	#1286260

On 08-12-15, 11:47, Viresh Kumar wrote:
> On 07-12-15, 19:18, Bartlomiej Zolnierkiewicz wrote:
> > Hi,
> > 
> > This patch series adds generic cpufreq-dt driver support for
> > Exynos542x/5800 (using the new CPU clock type which allows it).
> > 
> > It has been tested on Exynos5422 based ODROID-XU3 Lite board.
> 
> Excellent work Bartlomiej. Thanks a lot for adapting cpufreq-dt for
> this. Really appreciate it :)

You fix the oppXX@ problem and add my

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

for the entire series. Good work.

-- 
viresh
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#1287480

From	Javier Martinez Canillas <javier@osg.samsung.com>
Date	2015-12-09 14:20 +0100
Message-ID	<qDMOZ-qR-9@gated-at.bofh.it>
In reply to	#1285836

Hello Bartlomiej,

On 12/07/2015 03:18 PM, Bartlomiej Zolnierkiewicz wrote:
> Hi,
> 
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
> 
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>

I tested on an Exynos5800 Peach Pi and all governors are working
as expected on both the Cortex-A7 and Cortex-A15 cores.

So for the whole series:

Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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csiph-web

[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms

Contents

#1289039 — Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420

#1285850 — [PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock configuration data

#1286260

#1286266

#1287480