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[PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

Started byHarish Chegondi <harish.chegondi@intel.com>
First post2015-12-07 23:30 +0100
Last post2015-12-10 00:50 +0100
Articles 5 — 2 participants

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  [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing Harish Chegondi <harish.chegondi@intel.com> - 2015-12-07 23:30 +0100
    Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel  Knights Landing Peter Zijlstra <peterz@infradead.org> - 2015-12-08 09:40 +0100
      Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel  Knights Landing Harish Chegondi <harish.chegondi@intel.com> - 2015-12-10 00:30 +0100
        Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel  Knights Landing Peter Zijlstra <peterz@infradead.org> - 2015-12-10 00:40 +0100
          Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel  Knights Landing Harish Chegondi <harish.chegondi@intel.com> - 2015-12-10 00:50 +0100

#1286033 — [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

FromHarish Chegondi <harish.chegondi@intel.com>
Date2015-12-07 23:30 +0100
Subject[PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing
Message-ID<qDcsb-2fH-35@gated-at.bofh.it>
Knights Landing core is based on Silvermont core with several differences.
Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the
LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs
Unlike Silvermont, Knights Landing supports hyperthreading. Knights Landing
offcore response events config register mask is different from that of the
Silvermont.

This patch was developed based on a patch from Andi Kleen.

For more details, please refer to the public document:
https://software.intel.com/sites/default/files/managed/15/8d/IntelXeonPhi%E2%84%A2x200ProcessorPerformanceMonitoringReferenceManual_Volume1_Registers_v0%206.pdf

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
---
 arch/x86/kernel/cpu/perf_event.h           |  2 +
 arch/x86/kernel/cpu/perf_event_intel.c     | 62 ++++++++++++++++++++++++++++++
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 14 +++++++
 3 files changed, 78 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 799e6bd..dbaf026 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -901,6 +901,8 @@ void intel_pmu_lbr_init_hsw(void);
 
 void intel_pmu_lbr_init_skl(void);
 
+void intel_pmu_lbr_init_knl(void);
+
 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 
 void intel_pt_interrupt(void);
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 33b4b67..cf0a136 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -185,6 +185,14 @@ struct event_constraint intel_skl_event_constraints[] = {
 	EVENT_CONSTRAINT_END
 };
 
+static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
+	INTEL_UEVENT_EXTRA_REG(0x01b7,
+			       MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x02b7,
+			       MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
+	EVENT_EXTRA_END
+};
+
 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
@@ -1457,6 +1465,42 @@ static __initconst const u64 slm_hw_cache_event_ids
  },
 };
 
+#define KNL_OT_L2_HITE		BIT_ULL(19) /* Other Tile L2 Hit */
+#define KNL_OT_L2_HITF		BIT_ULL(20) /* Other Tile L2 Hit */
+#define KNL_MCDRAM_LOCAL	BIT_ULL(21)
+#define KNL_MCDRAM_FAR		BIT_ULL(22)
+#define KNL_DDR_LOCAL		BIT_ULL(23)
+#define KNL_DDR_FAR		BIT_ULL(24)
+#define KNL_DRAM_ANY		(KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
+				    KNL_DDR_LOCAL | KNL_DDR_FAR)
+#define KNL_L2_READ		SLM_DMND_READ
+#define KNL_L2_WRITE		SLM_DMND_WRITE
+#define KNL_L2_PREFETCH		SLM_DMND_PREFETCH
+#define KNL_L2_ACCESS		SLM_LLC_ACCESS
+#define KNL_L2_MISS		(KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
+				   KNL_DRAM_ANY | SNB_SNP_ANY | \
+						  SNB_NON_DRAM)
+
+static __initconst const u64 knl_hw_cache_extra_regs
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+	[C(LL)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
+			[C(RESULT_MISS)]   = 0,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
+			[C(RESULT_MISS)]   = KNL_L2_WRITE | KNL_L2_MISS,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
+			[C(RESULT_MISS)]   = KNL_L2_PREFETCH | KNL_L2_MISS,
+		},
+	},
+};
+
 /*
  * Use from PMIs where the LBRs are already disabled.
  */
@@ -3511,6 +3555,24 @@ __init int intel_pmu_init(void)
 		pr_cont("Broadwell events, ");
 		break;
 
+	case 87: /* Knights Landing Xeon Phi */
+		memcpy(hw_cache_event_ids,
+		       slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
+		memcpy(hw_cache_extra_regs,
+		       knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
+		intel_pmu_lbr_init_knl();
+
+		x86_pmu.event_constraints = intel_slm_event_constraints;
+		x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
+		x86_pmu.extra_regs = intel_knl_extra_regs;
+
+		/* all extra regs are per-cpu when HT is on */
+		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
+		x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
+
+		pr_cont("Knights Landing events, ");
+		break;
+
 	case 78: /* 14nm Skylake Mobile */
 	case 94: /* 14nm Skylake Desktop */
 		x86_pmu.late_ack = true;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index e2fad0c..50bf2de 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -1043,3 +1043,17 @@ void __init intel_pmu_lbr_init_atom(void)
 	 */
 	pr_cont("8-deep LBR, ");
 }
+
+/* Knights Landing */
+void intel_pmu_lbr_init_knl(void)
+{
+	x86_pmu.lbr_nr	   = 8;
+	x86_pmu.lbr_tos    = MSR_LBR_TOS;
+	x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;
+	x86_pmu.lbr_to     = MSR_LBR_NHM_TO;
+
+	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
+	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
+
+	pr_cont("8-deep LBR, ");
+}
-- 
2.1.2.330.g565301e

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#1286317 — Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

FromPeter Zijlstra <peterz@infradead.org>
Date2015-12-08 09:40 +0100
SubjectRe: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing
Message-ID<qDlYt-8lR-5@gated-at.bofh.it>
In reply to#1286033
On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote:
> Knights Landing core is based on Silvermont core with several differences.
> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the
> LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs


> +/* Knights Landing */
> +void intel_pmu_lbr_init_knl(void)
> +{
> +	x86_pmu.lbr_nr	   = 8;
> +	x86_pmu.lbr_tos    = MSR_LBR_TOS;
> +	x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;
> +	x86_pmu.lbr_to     = MSR_LBR_NHM_TO;
> +
> +	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
> +	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;

Also, unlike Silvermont, this thing seems to have hardware LBR filters.
So would it not be more accurate to say the KNL has a big core LBR
instead? (Note that this LBR setup isn't specific to Xeon's, all of the
Core chips have this, including the client parts).

> +	pr_cont("8-deep LBR, ");
> +}
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#1288048 — Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

FromHarish Chegondi <harish.chegondi@intel.com>
Date2015-12-10 00:30 +0100
SubjectRe: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing
Message-ID<qDWlm-6vk-61@gated-at.bofh.it>
In reply to#1286317

On 12/08/2015 12:37 AM, Peter Zijlstra wrote:
> On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote:
>> Knights Landing core is based on Silvermont core with several differences.
>> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the
>> LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs
>
>> +/* Knights Landing */
>> +void intel_pmu_lbr_init_knl(void)
>> +{
>> +	x86_pmu.lbr_nr	   = 8;
>> +	x86_pmu.lbr_tos    = MSR_LBR_TOS;
>> +	x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;
>> +	x86_pmu.lbr_to     = MSR_LBR_NHM_TO;
>> +
>> +	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
>> +	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
> Also, unlike Silvermont, this thing seems to have hardware LBR filters.
> So would it not be more accurate to say the KNL has a big core LBR
> instead? (Note that this LBR setup isn't specific to Xeon's, all of the
> Core chips have this, including the client parts).
We cannot say that KNL has a big core LBR. This is because architectural MSR IA32_PERF_CAPABILITIES[5:0] which indicates the format of the address that is stored in the LBR stack is different for KNL (IA32_PERF_CAPABILITIES[5:0] = 0x1) and big core (for example, Haswell IA32_PERF_CAPABILITIES[5:0]=0x4). Haswell LBR stack has TSX info which KNL LBR stack doesn't have.

Thanks for the review!

>
>> +	pr_cont("8-deep LBR, ");
>> +}
> .
>


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#1288059 — Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

FromPeter Zijlstra <peterz@infradead.org>
Date2015-12-10 00:40 +0100
SubjectRe: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing
Message-ID<qDWv0-6yV-13@gated-at.bofh.it>
In reply to#1288048
On Wed, Dec 09, 2015 at 03:22:29PM -0800, Harish Chegondi wrote:

> On 12/08/2015 12:37 AM, Peter Zijlstra wrote:
> > On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote:
> >> Knights Landing core is based on Silvermont core with several differences.
> >> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the
> >> LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs
> >
> >> +/* Knights Landing */
> >> +void intel_pmu_lbr_init_knl(void)
> >> +{
> >> +	x86_pmu.lbr_nr	   = 8;
> >> +	x86_pmu.lbr_tos    = MSR_LBR_TOS;
> >> +	x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;
> >> +	x86_pmu.lbr_to     = MSR_LBR_NHM_TO;
> >> +
> >> +	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
> >> +	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;

> > Also, unlike Silvermont, this thing seems to have hardware LBR filters.
> > So would it not be more accurate to say the KNL has a big core LBR
> > instead? (Note that this LBR setup isn't specific to Xeon's, all of the
> > Core chips have this, including the client parts).

> We cannot say that KNL has a big core LBR. This is because
> architectural MSR IA32_PERF_CAPABILITIES[5:0] which indicates the
> format of the address that is stored in the LBR stack is different for
> KNL (IA32_PERF_CAPABILITIES[5:0] = 0x1) and big core (for example,
> Haswell IA32_PERF_CAPABILITIES[5:0]=0x4). Haswell LBR stack has TSX
> info which KNL LBR stack doesn't have.

Fair enough I suppose. Applied the patch.
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#1288061 — Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

FromHarish Chegondi <harish.chegondi@intel.com>
Date2015-12-10 00:50 +0100
SubjectRe: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing
Message-ID<qDWEG-6Dw-5@gated-at.bofh.it>
In reply to#1288059

On 12/09/2015 03:37 PM, Peter Zijlstra wrote:
> On Wed, Dec 09, 2015 at 03:22:29PM -0800, Harish Chegondi wrote:
>
>> On 12/08/2015 12:37 AM, Peter Zijlstra wrote:
>>> On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote:
>>>> Knights Landing core is based on Silvermont core with several differences.
>>>> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the
>>>> LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs
>>>> +/* Knights Landing */
>>>> +void intel_pmu_lbr_init_knl(void)
>>>> +{
>>>> +	x86_pmu.lbr_nr	   = 8;
>>>> +	x86_pmu.lbr_tos    = MSR_LBR_TOS;
>>>> +	x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;
>>>> +	x86_pmu.lbr_to     = MSR_LBR_NHM_TO;
>>>> +
>>>> +	x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
>>>> +	x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
>>> Also, unlike Silvermont, this thing seems to have hardware LBR filters.
>>> So would it not be more accurate to say the KNL has a big core LBR
>>> instead? (Note that this LBR setup isn't specific to Xeon's, all of the
>>> Core chips have this, including the client parts).
>> We cannot say that KNL has a big core LBR. This is because
>> architectural MSR IA32_PERF_CAPABILITIES[5:0] which indicates the
>> format of the address that is stored in the LBR stack is different for
>> KNL (IA32_PERF_CAPABILITIES[5:0] = 0x1) and big core (for example,
>> Haswell IA32_PERF_CAPABILITIES[5:0]=0x4). Haswell LBR stack has TSX
>> info which KNL LBR stack doesn't have.
> Fair enough I suppose. Applied the patch.
> .
>
Thank you Peter!
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