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[PATCH 4.1 52/95] net: mvneta: Fix CPU_MAP registers initialisation

Started byGreg Kroah-Hartman <gregkh@linuxfoundation.org>
First post2015-12-07 15:50 +0100
Last post2015-12-07 15:50 +0100
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  [PATCH 4.1 52/95] net: mvneta: Fix CPU_MAP registers initialisation Greg Kroah-Hartman <gregkh@linuxfoundation.org> - 2015-12-07 15:50 +0100

#1285440 — [PATCH 4.1 52/95] net: mvneta: Fix CPU_MAP registers initialisation

FromGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Date2015-12-07 15:50 +0100
Subject[PATCH 4.1 52/95] net: mvneta: Fix CPU_MAP registers initialisation
Message-ID<qD5gZ-5PF-1@gated-at.bofh.it>
4.1-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Maxime Ripard <maxime.ripard@free-electrons.com>

commit 2502d0ef272da7058ef303b849a2c8dc324c2e2e upstream.

The CPU_MAP register is duplicated for each CPUs at different addresses,
each instance being at a different address.

However, the code so far was using CONFIG_NR_CPUS to initialise the CPU_MAP
registers for each registers, while the SoCs embed at most 4 CPUs.

This is especially an issue with multi_v7_defconfig, where CONFIG_NR_CPUS
is currently set to 16, resulting in writes to registers that are not
CPU_MAP.

Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network unit")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 drivers/net/ethernet/marvell/mvneta.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -949,7 +949,7 @@ static void mvneta_defaults_set(struct m
 	/* Set CPU queue access map - all CPUs have access to all RX
 	 * queues and to all TX queues
 	 */
-	for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
+	for_each_present_cpu(cpu)
 		mvreg_write(pp, MVNETA_CPU_MAP(cpu),
 			    (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
 			     MVNETA_CPU_TXQ_ACCESS_ALL_MASK));


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