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| Started by | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| First post | 2015-12-05 14:20 +0100 |
| Last post | 2015-12-07 10:30 +0100 |
| Articles | 2 — 2 participants |
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[PATCH resend 5/6] ARM: dts: sun7i: Add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2015-12-05 14:20 +0100
Re: [PATCH resend 5/6] ARM: dts: sun7i: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-12-07 10:30 +0100
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-12-05 14:20 +0100 |
| Subject | [PATCH resend 5/6] ARM: dts: sun7i: Add DRAM gates |
| Message-ID | <qCkUN-1wZ-19@gated-at.bofh.it> |
The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 32 +++++++++++++++++++++++++++++---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e02eb720c4fc..21169c0a6627 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -68,7 +68,7 @@
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>;
+ <&ahb_gates 44>, <&dram_gates 26>;
status = "disabled";
};
@@ -76,7 +76,8 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
+ <&dram_gates 26>;
status = "disabled";
};
@@ -85,7 +86,7 @@
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>;
+ <&ahb_gates 44>, <&dram_gates 26>;
status = "disabled";
};
};
@@ -501,6 +502,31 @@
clock-output-names = "spi3";
};
+ dram_gates: clk@01c20100 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-dram-gates-clk";
+ reg = <0x01c20100 0x4>;
+ clocks = <&pll5 0>;
+ clock-indices = <0>,
+ <1>, <2>,
+ <3>,
+ <4>,
+ <5>, <6>,
+ <15>,
+ <24>, <25>,
+ <26>, <27>,
+ <28>, <29>;
+ clock-output-names = "dram_ve",
+ "dram_csi0", "dram_csi1",
+ "dram_ts",
+ "dram_tvd",
+ "dram_tve0", "dram_tve1",
+ "dram_output",
+ "dram_de_fe1", "dram_de_fe0",
+ "dram_de_be0", "dram_de_be1",
+ "dram_de_mp", "dram_ace";
+ };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
--
2.6.2
--
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-12-07 10:30 +0100 |
| Message-ID | <qD0hl-2Dk-29@gated-at.bofh.it> |
| In reply to | #1284554 |
[Multipart message — attachments visible in raw view] — view raw
On Sat, Dec 05, 2015 at 09:16:46PM +0800, Chen-Yu Tsai wrote: > The DRAM gates controls direct memory access for some peripherals. > These peripherals include the display pipeline, so add the required > gates to the simplefb nodes as well. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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