Groups > linux.kernel > #1282600 > unrolled thread

[PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

Started by	Simon Arlott <simon@fire.lp0.eu>
First post	2015-12-03 00:50 +0100
Last post	2015-12-09 21:10 +0100
Articles	7 — 5 participants

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  [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding Simon Arlott <simon@fire.lp0.eu> - 2015-12-03 00:50 +0100
    [PATCH 2/3] mtd: brcmnand: Request and enable the clock if present Simon Arlott <simon@fire.lp0.eu> - 2015-12-03 00:50 +0100
      Re: [PATCH 2/3] mtd: brcmnand: Request and enable the clock if  present Brian Norris <computersforpeace@gmail.com> - 2015-12-03 01:20 +0100
    Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree  binding Rob Herring <robh@kernel.org> - 2015-12-04 16:10 +0100
    Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding Jonas Gorski <jogo@openwrt.org> - 2015-12-04 17:10 +0100
      Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree  binding "Simon Arlott" <simon@fire.lp0.eu> - 2015-12-04 22:40 +0100
        Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree  binding Brian Norris <computersforpeace@gmail.com> - 2015-12-09 21:10 +0100

#1282600 — [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

From	Simon Arlott <simon@fire.lp0.eu>
Date	2015-12-03 00:50 +0100
Subject	[PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding
Message-ID	<qBpjP-5xC-3@gated-at.bofh.it>

Add device tree binding for NAND on the BCM6368.

The BCM6368 has a NAND interrupt register with combined status and enable
registers. It also requires a clock, so add an optional clock to the
common brcmnand binding.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
---
Renamed from BCM63268, made clock a generic property.

 .../devicetree/bindings/mtd/brcm,brcmnand.txt      | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
index 4ff7128..16d7835 100644
--- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
+++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
@@ -45,6 +45,8 @@ Required properties:
 - #size-cells      : <0>
 
 Optional properties:
+- clock                     : reference to the clock for the NAND controller
+- clock-names               : "nand" (required for the above clock)
 - brcm,nand-has-wp          : Some versions of this IP include a write-protect
                               (WP) control bit. It is always available on >=
                               v7.0. Use this property to describe the rare
@@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w
        and enable registers
      - reg-names: (required) "nand-int-base"
 
+   * "brcm,nand-bcm6368"
+     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
+     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
+       and enable registers, and boot address registers
+     - reg-names: (required) "nand-intr-base"
+
    * "brcm,nand-iproc"
      - reg: (required) the "IDM" register range, for interrupt enable and APB
        bus access endianness configuration, and the "EXT" register range,
@@ -148,3 +156,27 @@ nand@f0442800 {
 		};
 	};
 };
+
+nand@10000200 {
+	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
+		"brcm,brcmnand-v4.0", "brcm,brcmnand";
+	reg = <0x10000200 0x180>,
+	      <0x10000600 0x200>,
+	      <0x100000b0 0x10>;
+	reg-names = "nand", "nand-cache", "nand-intr-base";
+	interrupt-parent = <&periph_intc>;
+	interrupts = <50>;
+	clocks = <&periph_clk 20>;
+	clock-names = "nand";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nand0: nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-on-flash-bbt;
+		nand-ecc-strength = <1>;
+		nand-ecc-step-size = <512>;
+	};
+};
-- 
2.1.4

-- 
Simon Arlott
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#1282604 — [PATCH 2/3] mtd: brcmnand: Request and enable the clock if present

From	Simon Arlott <simon@fire.lp0.eu>
Date	2015-12-03 00:50 +0100
Subject	[PATCH 2/3] mtd: brcmnand: Request and enable the clock if present
Message-ID	<qBpjQ-5xC-21@gated-at.bofh.it>
In reply to	#1282600

Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
---
 drivers/mtd/nand/brcmnand/brcmnand.c | 69 ++++++++++++++++++++++++++++--------
 1 file changed, 54 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c
index 2c8f67f..0a9cccf 100644
--- a/drivers/mtd/nand/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/brcmnand/brcmnand.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/clk.h>
 #include <linux/version.h>
 #include <linux/module.h>
 #include <linux/init.h>
@@ -122,6 +123,9 @@ struct brcmnand_controller {
 	/* Some SoCs provide custom interrupt status register(s) */
 	struct brcmnand_soc	*soc;
 
+	/* Some SoCs have a gateable clock for the controller */
+	struct clk		*clk;
+
 	int			cmd_pending;
 	bool			dma_pending;
 	struct completion	done;
@@ -2136,10 +2140,24 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 	if (IS_ERR(ctrl->nand_base))
 		return PTR_ERR(ctrl->nand_base);
 
+	/* Enable clock before using NAND registers */
+	ctrl->clk = devm_clk_get(dev, "nand");
+	if (!IS_ERR(ctrl->clk)) {
+		ret = clk_prepare_enable(ctrl->clk);
+		if (ret)
+			return ret;
+	} else {
+		ret = PTR_ERR(ctrl->clk);
+		if (ret == -EPROBE_DEFER)
+			return ret;
+
+		ctrl->clk = NULL;
+	}
+
 	/* Initialize NAND revision */
 	ret = brcmnand_revision_init(ctrl);
 	if (ret)
-		return ret;
+		goto err;
 
 	/*
 	 * Most chips have this cache at a fixed offset within 'nand' block.
@@ -2148,8 +2166,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
 	if (res) {
 		ctrl->nand_fc = devm_ioremap_resource(dev, res);
-		if (IS_ERR(ctrl->nand_fc))
-			return PTR_ERR(ctrl->nand_fc);
+		if (IS_ERR(ctrl->nand_fc)) {
+			ret = PTR_ERR(ctrl->nand_fc);
+			goto err;
+		}
 	} else {
 		ctrl->nand_fc = ctrl->nand_base +
 				ctrl->reg_offsets[BRCMNAND_FC_BASE];
@@ -2159,8 +2179,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
 	if (res) {
 		ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
-		if (IS_ERR(ctrl->flash_dma_base))
-			return PTR_ERR(ctrl->flash_dma_base);
+		if (IS_ERR(ctrl->flash_dma_base)) {
+			ret = PTR_ERR(ctrl->flash_dma_base);
+			goto err;
+		}
 
 		flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
 		flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
@@ -2169,13 +2191,16 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 		ctrl->dma_desc = dmam_alloc_coherent(dev,
 						     sizeof(*ctrl->dma_desc),
 						     &ctrl->dma_pa, GFP_KERNEL);
-		if (!ctrl->dma_desc)
-			return -ENOMEM;
+		if (!ctrl->dma_desc) {
+			ret = -ENOMEM;
+			goto err;
+		}
 
 		ctrl->dma_irq = platform_get_irq(pdev, 1);
 		if ((int)ctrl->dma_irq < 0) {
 			dev_err(dev, "missing FLASH_DMA IRQ\n");
-			return -ENODEV;
+			ret = -ENODEV;
+			goto err;
 		}
 
 		ret = devm_request_irq(dev, ctrl->dma_irq,
@@ -2184,7 +2209,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 		if (ret < 0) {
 			dev_err(dev, "can't allocate IRQ %d: error %d\n",
 					ctrl->dma_irq, ret);
-			return ret;
+			goto err;
 		}
 
 		dev_info(dev, "enabling FLASH_DMA\n");
@@ -2208,7 +2233,8 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 	ctrl->irq = platform_get_irq(pdev, 0);
 	if ((int)ctrl->irq < 0) {
 		dev_err(dev, "no IRQ defined\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err;
 	}
 
 	/*
@@ -2232,7 +2258,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 	if (ret < 0) {
 		dev_err(dev, "can't allocate IRQ %d: error %d\n",
 			ctrl->irq, ret);
-		return ret;
+		goto err;
 	}
 
 	for_each_available_child_of_node(dn, child) {
@@ -2240,8 +2266,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 			struct brcmnand_host *host;
 
 			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
-			if (!host)
-				return -ENOMEM;
+			if (!host) {
+				ret = -ENOMEM;
+				goto err;
+			}
 			host->pdev = pdev;
 			host->ctrl = ctrl;
 			host->of_node = child;
@@ -2255,10 +2283,18 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
 	}
 
 	/* No chip-selects could initialize properly */
-	if (list_empty(&ctrl->host_list))
-		return -ENODEV;
+	if (list_empty(&ctrl->host_list)) {
+		ret = -ENODEV;
+		goto err;
+	}
 
 	return 0;
+
+err:
+	if (ctrl->clk)
+		clk_disable_unprepare(ctrl->clk);
+	return ret;
+
 }
 EXPORT_SYMBOL_GPL(brcmnand_probe);
 
@@ -2270,6 +2306,9 @@ int brcmnand_remove(struct platform_device *pdev)
 	list_for_each_entry(host, &ctrl->host_list, node)
 		nand_release(&host->mtd);
 
+	if (ctrl->clk)
+		clk_disable_unprepare(ctrl->clk);
+
 	dev_set_drvdata(&pdev->dev, NULL);
 
 	return 0;
-- 
2.1.4

-- 
Simon Arlott
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#1282616 — Re: [PATCH 2/3] mtd: brcmnand: Request and enable the clock if present

From	Brian Norris <computersforpeace@gmail.com>
Date	2015-12-03 01:20 +0100
Subject	Re: [PATCH 2/3] mtd: brcmnand: Request and enable the clock if present
Message-ID	<qBpMR-5Y5-1@gated-at.bofh.it>
In reply to	#1282604

Hi Simon,

On Wed, Dec 02, 2015 at 11:42:44PM +0000, Simon Arlott wrote:
> Attempt to enable a clock named "nand" as some SoCs have a clock for the
> controller that needs to be enabled.
> 
> Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
> ---
>  drivers/mtd/nand/brcmnand/brcmnand.c | 69 ++++++++++++++++++++++++++++--------
>  1 file changed, 54 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c
> index 2c8f67f..0a9cccf 100644
> --- a/drivers/mtd/nand/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/brcmnand/brcmnand.c
> @@ -11,6 +11,7 @@
>   * GNU General Public License for more details.
>   */
>  
> +#include <linux/clk.h>
>  #include <linux/version.h>
>  #include <linux/module.h>
>  #include <linux/init.h>
> @@ -122,6 +123,9 @@ struct brcmnand_controller {
>  	/* Some SoCs provide custom interrupt status register(s) */
>  	struct brcmnand_soc	*soc;
>  
> +	/* Some SoCs have a gateable clock for the controller */
> +	struct clk		*clk;
> +
>  	int			cmd_pending;
>  	bool			dma_pending;
>  	struct completion	done;
> @@ -2136,10 +2140,24 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  	if (IS_ERR(ctrl->nand_base))
>  		return PTR_ERR(ctrl->nand_base);
>  
> +	/* Enable clock before using NAND registers */
> +	ctrl->clk = devm_clk_get(dev, "nand");
> +	if (!IS_ERR(ctrl->clk)) {
> +		ret = clk_prepare_enable(ctrl->clk);
> +		if (ret)
> +			return ret;
> +	} else {
> +		ret = PTR_ERR(ctrl->clk);
> +		if (ret == -EPROBE_DEFER)
> +			return ret;
> +
> +		ctrl->clk = NULL;
> +	}
> +
>  	/* Initialize NAND revision */
>  	ret = brcmnand_revision_init(ctrl);
>  	if (ret)
> -		return ret;
> +		goto err;
>  
>  	/*
>  	 * Most chips have this cache at a fixed offset within 'nand' block.
> @@ -2148,8 +2166,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
>  	if (res) {
>  		ctrl->nand_fc = devm_ioremap_resource(dev, res);
> -		if (IS_ERR(ctrl->nand_fc))
> -			return PTR_ERR(ctrl->nand_fc);
> +		if (IS_ERR(ctrl->nand_fc)) {
> +			ret = PTR_ERR(ctrl->nand_fc);
> +			goto err;
> +		}
>  	} else {
>  		ctrl->nand_fc = ctrl->nand_base +
>  				ctrl->reg_offsets[BRCMNAND_FC_BASE];
> @@ -2159,8 +2179,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
>  	if (res) {
>  		ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
> -		if (IS_ERR(ctrl->flash_dma_base))
> -			return PTR_ERR(ctrl->flash_dma_base);
> +		if (IS_ERR(ctrl->flash_dma_base)) {
> +			ret = PTR_ERR(ctrl->flash_dma_base);
> +			goto err;
> +		}
>  
>  		flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
>  		flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
> @@ -2169,13 +2191,16 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  		ctrl->dma_desc = dmam_alloc_coherent(dev,
>  						     sizeof(*ctrl->dma_desc),
>  						     &ctrl->dma_pa, GFP_KERNEL);
> -		if (!ctrl->dma_desc)
> -			return -ENOMEM;
> +		if (!ctrl->dma_desc) {
> +			ret = -ENOMEM;
> +			goto err;
> +		}
>  
>  		ctrl->dma_irq = platform_get_irq(pdev, 1);
>  		if ((int)ctrl->dma_irq < 0) {
>  			dev_err(dev, "missing FLASH_DMA IRQ\n");
> -			return -ENODEV;
> +			ret = -ENODEV;
> +			goto err;
>  		}
>  
>  		ret = devm_request_irq(dev, ctrl->dma_irq,
> @@ -2184,7 +2209,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  		if (ret < 0) {
>  			dev_err(dev, "can't allocate IRQ %d: error %d\n",
>  					ctrl->dma_irq, ret);
> -			return ret;
> +			goto err;
>  		}
>  
>  		dev_info(dev, "enabling FLASH_DMA\n");
> @@ -2208,7 +2233,8 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  	ctrl->irq = platform_get_irq(pdev, 0);
>  	if ((int)ctrl->irq < 0) {
>  		dev_err(dev, "no IRQ defined\n");
> -		return -ENODEV;
> +		ret = -ENODEV;
> +		goto err;
>  	}
>  
>  	/*
> @@ -2232,7 +2258,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  	if (ret < 0) {
>  		dev_err(dev, "can't allocate IRQ %d: error %d\n",
>  			ctrl->irq, ret);
> -		return ret;
> +		goto err;
>  	}
>  
>  	for_each_available_child_of_node(dn, child) {
> @@ -2240,8 +2266,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  			struct brcmnand_host *host;
>  
>  			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> -			if (!host)
> -				return -ENOMEM;
> +			if (!host) {
> +				ret = -ENOMEM;
> +				goto err;
> +			}
>  			host->pdev = pdev;
>  			host->ctrl = ctrl;
>  			host->of_node = child;

Please submit against l2-mtd.git or linux-next.git:

http://linux-mtd.infradead.org/source.html

> @@ -2255,10 +2283,18 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
>  	}
>  
>  	/* No chip-selects could initialize properly */
> -	if (list_empty(&ctrl->host_list))
> -		return -ENODEV;
> +	if (list_empty(&ctrl->host_list)) {
> +		ret = -ENODEV;
> +		goto err;
> +	}
>  
>  	return 0;
> +
> +err:
> +	if (ctrl->clk)

This NULL check is unnecessary.

> +		clk_disable_unprepare(ctrl->clk);
> +	return ret;
> +
>  }
>  EXPORT_SYMBOL_GPL(brcmnand_probe);
>  
> @@ -2270,6 +2306,9 @@ int brcmnand_remove(struct platform_device *pdev)
>  	list_for_each_entry(host, &ctrl->host_list, node)
>  		nand_release(&host->mtd);
>  
> +	if (ctrl->clk)

Same here.

> +		clk_disable_unprepare(ctrl->clk);
> +
>  	dev_set_drvdata(&pdev->dev, NULL);
>  
>  	return 0;

Otherwise, LGTM.

Brian
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#1283897 — Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

From	Rob Herring <robh@kernel.org>
Date	2015-12-04 16:10 +0100
Subject	Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding
Message-ID	<qC09I-4m0-17@gated-at.bofh.it>
In reply to	#1282600

On Wed, Dec 02, 2015 at 11:41:26PM +0000, Simon Arlott wrote:
> Add device tree binding for NAND on the BCM6368.
> 
> The BCM6368 has a NAND interrupt register with combined status and enable
> registers. It also requires a clock, so add an optional clock to the
> common brcmnand binding.
> 
> Signed-off-by: Simon Arlott <simon@fire.lp0.eu>

Acked-by: Rob Herring <robh@kernel.org>

> ---
> Renamed from BCM63268, made clock a generic property.
> 
>  .../devicetree/bindings/mtd/brcm,brcmnand.txt      | 32 ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> index 4ff7128..16d7835 100644
> --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> @@ -45,6 +45,8 @@ Required properties:
>  - #size-cells      : <0>
>  
>  Optional properties:
> +- clock                     : reference to the clock for the NAND controller
> +- clock-names               : "nand" (required for the above clock)
>  - brcm,nand-has-wp          : Some versions of this IP include a write-protect
>                                (WP) control bit. It is always available on >=
>                                v7.0. Use this property to describe the rare
> @@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w
>         and enable registers
>       - reg-names: (required) "nand-int-base"
>  
> +   * "brcm,nand-bcm6368"
> +     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
> +     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
> +       and enable registers, and boot address registers
> +     - reg-names: (required) "nand-intr-base"
> +
>     * "brcm,nand-iproc"
>       - reg: (required) the "IDM" register range, for interrupt enable and APB
>         bus access endianness configuration, and the "EXT" register range,
> @@ -148,3 +156,27 @@ nand@f0442800 {
>  		};
>  	};
>  };
> +
> +nand@10000200 {
> +	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
> +		"brcm,brcmnand-v4.0", "brcm,brcmnand";
> +	reg = <0x10000200 0x180>,
> +	      <0x10000600 0x200>,
> +	      <0x100000b0 0x10>;
> +	reg-names = "nand", "nand-cache", "nand-intr-base";
> +	interrupt-parent = <&periph_intc>;
> +	interrupts = <50>;
> +	clocks = <&periph_clk 20>;
> +	clock-names = "nand";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nand0: nandcs@0 {
> +		compatible = "brcm,nandcs";
> +		reg = <0>;
> +		nand-on-flash-bbt;
> +		nand-ecc-strength = <1>;
> +		nand-ecc-step-size = <512>;
> +	};
> +};
> -- 
> 2.1.4
> 
> -- 
> Simon Arlott
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#1283968

From	Jonas Gorski <jogo@openwrt.org>
Date	2015-12-04 17:10 +0100
Message-ID	<qC15M-4Xp-17@gated-at.bofh.it>
In reply to	#1282600

On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <simon@fire.lp0.eu> wrote:
> Add device tree binding for NAND on the BCM6368.
>
> The BCM6368 has a NAND interrupt register with combined status and enable
> registers. It also requires a clock, so add an optional clock to the
> common brcmnand binding.
>
> Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
> ---
> Renamed from BCM63268, made clock a generic property.
>
>  .../devicetree/bindings/mtd/brcm,brcmnand.txt      | 32 ++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> index 4ff7128..16d7835 100644
> --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
> @@ -45,6 +45,8 @@ Required properties:
>  - #size-cells      : <0>
>
>  Optional properties:
> +- clock                     : reference to the clock for the NAND controller
> +- clock-names               : "nand" (required for the above clock)
>  - brcm,nand-has-wp          : Some versions of this IP include a write-protect
>                                (WP) control bit. It is always available on >=
>                                v7.0. Use this property to describe the rare
> @@ -72,6 +74,12 @@ we define additional 'compatible' properties and associated register resources w
>         and enable registers
>       - reg-names: (required) "nand-int-base"
>
> +   * "brcm,nand-bcm6368"
> +     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
> +     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
> +       and enable registers, and boot address registers
> +     - reg-names: (required) "nand-intr-base"

Can't we use the same name as bcm63138, i.e. nand-int-base?

> +
>     * "brcm,nand-iproc"
>       - reg: (required) the "IDM" register range, for interrupt enable and APB
>         bus access endianness configuration, and the "EXT" register range,
> @@ -148,3 +156,27 @@ nand@f0442800 {
>                 };
>         };
>  };
> +
> +nand@10000200 {
> +       compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
> +               "brcm,brcmnand-v4.0", "brcm,brcmnand";

I know it's now much too late, but this is IMHO a very odd way of
defining that this is a v4 nand, but uses bcm6368 compatible
interrupts, as bcm6368 is a much older, unsupported nand revision.


Jonas
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#1284250 — Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

From	"Simon Arlott" <simon@fire.lp0.eu>
Date	2015-12-04 22:40 +0100
Subject	Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding
Message-ID	<qC6f8-88D-27@gated-at.bofh.it>
In reply to	#1283968

On Fri, December 4, 2015 16:04, Jonas Gorski wrote:
> On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <simon@fire.lp0.eu> wrote:
>> +   * "brcm,nand-bcm6368"
>> +     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
>> +     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
>> +       and enable registers, and boot address registers
>> +     - reg-names: (required) "nand-intr-base"
>
> Can't we use the same name as bcm63138, i.e. nand-int-base?

Brian,

Before I change this, is there anything else in the patch series that needs to
be changed?

(I'll keep the comment referring to "NAND_INTR_BASE" the same because that's the name
in the original #define for this hardware.)

-- 
Simon Arlott
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#1287805 — Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

From	Brian Norris <computersforpeace@gmail.com>
Date	2015-12-09 21:10 +0100
Subject	Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding
Message-ID	<qDTdN-4yA-27@gated-at.bofh.it>
In reply to	#1284250

On Fri, Dec 04, 2015 at 09:29:55PM -0000, Simon Arlott wrote:
> On Fri, December 4, 2015 16:04, Jonas Gorski wrote:
> > On Thu, Dec 3, 2015 at 12:41 AM, Simon Arlott <simon@fire.lp0.eu> wrote:
> >> +   * "brcm,nand-bcm6368"
> >> +     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
> >> +     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
> >> +       and enable registers, and boot address registers
> >> +     - reg-names: (required) "nand-intr-base"
> >
> > Can't we use the same name as bcm63138, i.e. nand-int-base?
> 
> Brian,
> 
> Before I change this, is there anything else in the patch series that needs to
> be changed?

No, I think you covered my comments in your latest series:

http://lists.infradead.org/pipermail/linux-mtd/2015-December/064004.html

I don't know about Jonas's comments about using bcm6368, even though
bcm6368 is a much older NAND core. I had similar thoughts when Florian
first proposed it, but I'm not sure I have a much better suggestion.
We're trying to describe two slightly different tracks of IP: the core
NAND controller, which has a defined revision (2.x, 4.0, etc.), and the
accessory interrupt bits, which are mostly constant across a product
line / class of SoCs and aren't really versioned.

So I guess I'm OK with the usage of the bcm6368 compatible string.

Regards,
Brian
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csiph-web

[PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

Contents

#1282600 — [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

#1282604 — [PATCH 2/3] mtd: brcmnand: Request and enable the clock if present

#1282616 — Re: [PATCH 2/3] mtd: brcmnand: Request and enable the clock if present

#1283897 — Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

#1283968

#1284250 — Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding

#1287805 — Re: [PATCH 1/3] mtd: brcmnand: Add brcm,bcm6368-nand device tree binding