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| Started by | Simon Arlott <simon@fire.lp0.eu> |
|---|---|
| First post | 2015-11-30 22:00 +0100 |
| Last post | 2015-12-08 13:30 +0100 |
| Articles | 5 — 4 participants |
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[PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding Simon Arlott <simon@fire.lp0.eu> - 2015-11-30 22:00 +0100
Re: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding Florian Fainelli <f.fainelli@gmail.com> - 2015-12-02 19:20 +0100
Re: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding Rob Herring <robh@kernel.org> - 2015-12-04 15:40 +0100
Re: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding "Simon Arlott" <simon@fire.lp0.eu> - 2015-12-04 22:10 +0100
Re: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding "Simon Arlott" <simon@fire.lp0.eu> - 2015-12-08 13:30 +0100
| From | Simon Arlott <simon@fire.lp0.eu> |
|---|---|
| Date | 2015-11-30 22:00 +0100 |
| Subject | [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding |
| Message-ID | <qADIe-8wf-11@gated-at.bofh.it> |
Add device tree binding for the BCM63xx's gated clocks.
The BCM63xx contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
---
.../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
new file mode 100644
index 0000000..3f4ead1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
@@ -0,0 +1,58 @@
+Broadcom BCM63xx clocks
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The BCM63xx contains clocks gated with a register. Clocks are indexed
+by bits in the register and are active high. Clock gate bits are
+interleaved with other status bits and configurable clocks in the same
+register.
+
+Required properties:
+- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk"
+- #clock-cells: Should be <1>.
+- regmap: The register map phandle
+- offset: Offset in the register map for the reboot register (in bytes)
+- clocks: The external oscillator clock phandle
+
+Example:
+
+periph_clk: periph_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
+ regmap = <&periph_cntl>;
+ offset = <0x4>;
+
+ #clock-cells = <1>;
+ clock-indices =
+ <1>, <2>, <3>, <4>, <5>,
+ <6>, <7>, <8>, <9>, <10>,
+ <11>, <12>, <13>, <14>, <15>,
+ <16>, <17>, <18>, <19>, <20>,
+ <27>, <31>;
+ clock-output-names =
+ "vdsl_qproc", "vdsl_afe", "vdsl", "mips", "wlan_ocp",
+ "dect", "fap0", "fap1", "sar", "robosw",
+ "pcm", "usbd", "usbh", "ipsec", "spi",
+ "hsspi", "pcie", "phymips", "gmac", "nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
+ regmap = <&timer_cntl>;
+ offset = <0x4>;
+
+ #clock-cells = <1>;
+ clock-indices = <17>, <18>;
+ clock-output-names = "uto_extin", "usb_ref";
+};
+
+ehci0: usb@10002500 {
+ compatible = "brcm,bcm63168-ehci", "brcm,bcm63xx-ehci", "generic-ehci";
+ reg = <0x10002500 0x100>;
+ big-endian;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <10>;
+ clocks = <&periph_clk 13>, <&timer_clk 18>;
+ phys = <&usbh>;
+};
--
2.1.4
--
Simon Arlott
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| From | Florian Fainelli <f.fainelli@gmail.com> |
|---|---|
| Date | 2015-12-02 19:20 +0100 |
| Message-ID | <qBkau-2mS-13@gated-at.bofh.it> |
| In reply to | #1280280 |
2015-11-30 12:52 GMT-08:00 Simon Arlott <simon@fire.lp0.eu>: > Add device tree binding for the BCM63xx's gated clocks. > > The BCM63xx contains clocks gated with a register. Clocks are indexed > by bits in the register and are active high. Clock gate bits are > interleaved with other status bits and configurable clocks in the same > register. > > Signed-off-by: Simon Arlott <simon@fire.lp0.eu> > --- > .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > > diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > new file mode 100644 > index 0000000..3f4ead1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt > @@ -0,0 +1,58 @@ > +Broadcom BCM63xx clocks > + > +This binding uses the common clock binding: > + Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +The BCM63xx contains clocks gated with a register. Clocks are indexed > +by bits in the register and are active high. Clock gate bits are > +interleaved with other status bits and configurable clocks in the same > +register. Most MIPS-based BCM63xx SoCs have clock gating set of registers, these SoCs are pretty much all of them except 63381 (maybe newer ones too), this one uses the PMB interface, like 63138 to control resets and clocks fed to peripherals. > + > +Required properties: > +- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk" I think we would want to start with the lowest common denominator here, which is either 6345 or 6348. -- Florian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-12-04 15:40 +0100 |
| Message-ID | <qBZGG-3Ud-21@gated-at.bofh.it> |
| In reply to | #1280280 |
On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
> Add device tree binding for the BCM63xx's gated clocks.
>
> The BCM63xx contains clocks gated with a register. Clocks are indexed
> by bits in the register and are active high. Clock gate bits are
> interleaved with other status bits and configurable clocks in the same
> register.
>
> Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
> ---
> .../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
> new file mode 100644
> index 0000000..3f4ead1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
> @@ -0,0 +1,58 @@
> +Broadcom BCM63xx clocks
> +
> +This binding uses the common clock binding:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +The BCM63xx contains clocks gated with a register. Clocks are indexed
> +by bits in the register and are active high. Clock gate bits are
> +interleaved with other status bits and configurable clocks in the same
> +register.
> +
> +Required properties:
> +- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk"
> +- #clock-cells: Should be <1>.
> +- regmap: The register map phandle
> +- offset: Offset in the register map for the reboot register (in bytes)
> +- clocks: The external oscillator clock phandle
> +
> +Example:
> +
> +periph_clk: periph_clk {
> + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
> + regmap = <&periph_cntl>;
What else is in periph_cntrl? Could this all just be part of that node?
Rob
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| From | "Simon Arlott" <simon@fire.lp0.eu> |
|---|---|
| Date | 2015-12-04 22:10 +0100 |
| Message-ID | <qC5M5-7Yp-7@gated-at.bofh.it> |
| In reply to | #1283871 |
On Fri, December 4, 2015 14:30, Rob Herring wrote:
> On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
>> +periph_clk: periph_clk {
>> + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
>> + regmap = <&periph_cntl>;
>
> What else is in periph_cntrl? Could this all just be part of that node?
uint32 RevID; /* (00) word 0 */
uint32 blkEnables; /* (04) word 1 */ <-- gated clocks
uint32 pll_control; /* (08) word 2 */ <-- system reset controller bit
uint32 deviceTimeoutEn; /* (0c) word 3 */ <-- unknown
uint32 softResetB; /* (10) word 4 */ <-- device reset controller bits
uint32 diagControl; /* (14) word 5 */ <-- unknown
uint32 ExtIrqCfg; /* (18) word 6*/ <-- external interrupt controller
uint32 unused1; /* (1c) word 7 */ <-- (external interrupt controller?)
IrqControl_t IrqControl[3]; /* (20) (40) (60) */ <-- normal interrupt controller
So it has these clocks, two types of reset controller, and the interrupt
controllers, but I've left the interrupt controllers registers out of the
syscon device.
For the registers in the "timer" peripheral at the end of the timer/watchdog
registers:
uint32 EnSwPLL; <-- unknown
uint32 ClkRstCtl;
#define POR_RESET_STATUS (1 << 31) <-- unknown
#define HW_RESET_STATUS (1 << 30) <-- unknown
#define SW_RESET_STATUS (1 << 29) <-- unknown
#define USB_REF_CLKEN (1 << 18) <-- gated clock
#define UTO_EXTIN_CLKEN (1 << 17) <-- gated clock
#define UTO_CLK50_SEL (1 << 16) <-- looks like a clock frequency selection bit
#define FAP2_PLL_CLKEN (1 << 15) <-- gated clock
#define FAP2_PLL_FREQ_SHIFT 12 <-- bits for controlling the frequency
#define FAP1_PLL_CLKEN (1 << 11) <-- gated clock
#define FAP1_PLL_FREQ_SHIFT 8 <-- bits for controlling the frequency
#define WAKEON_DSL (1 << 7) <-- wake on network bit
#define WAKEON_EPHY (1 << 6) <-- wake on network bit
#define DSL_ENERGY_DETECT_ENABLE (1 << 4) <-- energy saving control for network
#define GPHY_1_ENERGY_DETECT_ENABLE (1 << 3) <-- energy saving control for network
#define EPHY_3_ENERGY_DETECT_ENABLE (1 << 2) <-- energy saving control for network
#define EPHY_2_ENERGY_DETECT_ENABLE (1 << 1) <-- energy saving control for network
#define EPHY_1_ENERGY_DETECT_ENABLE (1 << 0) <-- energy saving control for network
I need the usb_ref clock for USB, and I want to be able to disable
uto_extin, fap1 and fap2 as they're unused by anything in the device tree.
The full list of registers is here:
https://github.com/lp0/bcm963xx_4.12L.06B_consumer/blob/master/shared/opensource/include/bcm963xx/63268_map_part.h
--
Simon Arlott
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| From | "Simon Arlott" <simon@fire.lp0.eu> |
|---|---|
| Date | 2015-12-08 13:30 +0100 |
| Message-ID | <qDpz3-2iu-5@gated-at.bofh.it> |
| In reply to | #1284228 |
On Fri, December 4, 2015 21:04, Simon Arlott wrote:
> On Fri, December 4, 2015 14:30, Rob Herring wrote:
>> On Mon, Nov 30, 2015 at 08:52:55PM +0000, Simon Arlott wrote:
>>> +periph_clk: periph_clk {
>>> + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
>>> + regmap = <&periph_cntl>;
>>
>> What else is in periph_cntrl? Could this all just be part of that node?
>
> uint32 RevID; /* (00) word 0 */
> uint32 blkEnables; /* (04) word 1 */ <-- gated clocks
> uint32 pll_control; /* (08) word 2 */ <-- system reset controller bit
> uint32 deviceTimeoutEn; /* (0c) word 3 */ <-- unknown
> uint32 softResetB; /* (10) word 4 */ <-- device reset controller bits
> uint32 diagControl; /* (14) word 5 */ <-- unknown
> uint32 ExtIrqCfg; /* (18) word 6*/ <-- external interrupt controller
> uint32 unused1; /* (1c) word 7 */ <-- (external interrupt controller?)
> IrqControl_t IrqControl[3]; /* (20) (40) (60) */ <-- normal interrupt controller
On the BCM6368 [1], blkEnables also conatains a power domain bit:
uint32 blkEnables; /* (04) word 1 */
#define USBH_IDDQ_EN (1 << 19)
#define IPSEC_CLK_EN (1 << 18)
#define NAND_CLK_EN (1 << 17)
#define DISABLE_GLESS (1 << 16)
#define USBH_CLK_EN (1 << 15)
#define PCM_CLK_EN (1 << 14)
#define UTOPIA_CLK_EN (1 << 13)
#define ROBOSW_CLK_EN (1 << 12)
#define SAR_CLK_EN (1 << 11)
#define USBD_CLK_EN (1 << 10)
#define SPI_CLK_EN (1 << 9)
#define SWPKT_SAR_CLK_EN (1 << 8)
#define SWPKT_USB_CLK_EN (1 << 7)
#define PHYMIPS_CLK_EN (1 << 6)
#define VDSL_CLK_EN (1 << 5)
#define VDSL_BONDING_EN (1 << 4)
#define VDSL_AFE_EN (1 << 3)
#define VDSL_QPROC_EN (1 << 2)
In order to be able to map these to devices for the BCM63xx SoCs I'm going
to define the power controller binding with "power-domain-indices" and
"power-domain-names" to mirror the clock binding. The separate clk and
generic_pm_domain devices will then handle set/clear of the relevant bits
using the regmap.
[1]
https://code.google.com/p/gfiber-gflt100/source/browse/shared/opensource/include/bcm963xx/6368_map_part.h?r=b292e8c271addbda62104bece90e3c8018714194
--
Simon Arlott
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