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[RESEND PATCH] arm64: bpf: add 'store immediate' instruction

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  [RESEND PATCH] arm64: bpf: add 'store immediate' instruction Yang Shi <yang.shi@linaro.org> - 2015-11-30 23:50 +0100
    Re: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction "Shi, Yang" <yang.shi@linaro.org> - 2015-12-01 23:30 +0100
      Re: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction Will Deacon <will.deacon@arm.com> - 2015-12-02 10:20 +0100
        Re: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction David Miller <davem@davemloft.net> - 2015-12-02 21:50 +0100
    Re: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction David Miller <davem@davemloft.net> - 2015-12-03 17:40 +0100

#1280383 — [RESEND PATCH] arm64: bpf: add 'store immediate' instruction

aarch64 doesn't have native store immediate instruction, such operation
has to be implemented by the below instruction sequence:

Load immediate to register
Store register

Signed-off-by: Yang Shi <yang.shi@linaro.org>
CC: Zi Shen Lim <zlim.lnx@gmail.com>
CC: Xi Wang <xi.wang@gmail.com>
---
Thsi patch might be buried by the storm of xadd discussion, however, it is
absolutely irrelevent to xadd, so resend the patch itself.

 arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 6809647..49c1f1b 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -563,7 +563,25 @@ emit_cond_jmp:
 	case BPF_ST | BPF_MEM | BPF_H:
 	case BPF_ST | BPF_MEM | BPF_B:
 	case BPF_ST | BPF_MEM | BPF_DW:
-		goto notyet;
+		/* Load imm to a register then store it */
+		ctx->tmp_used = 1;
+		emit_a64_mov_i(1, tmp2, off, ctx);
+		emit_a64_mov_i(1, tmp, imm, ctx);
+		switch (BPF_SIZE(code)) {
+		case BPF_W:
+			emit(A64_STR32(tmp, dst, tmp2), ctx);
+			break;
+		case BPF_H:
+			emit(A64_STRH(tmp, dst, tmp2), ctx);
+			break;
+		case BPF_B:
+			emit(A64_STRB(tmp, dst, tmp2), ctx);
+			break;
+		case BPF_DW:
+			emit(A64_STR64(tmp, dst, tmp2), ctx);
+			break;
+		}
+		break;
 
 	/* STX: *(size *)(dst + off) = src */
 	case BPF_STX | BPF_MEM | BPF_W:
-- 
2.0.2

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#1281263

On 11/30/2015 2:24 PM, Yang Shi wrote:
> aarch64 doesn't have native store immediate instruction, such operation
> has to be implemented by the below instruction sequence:
>
> Load immediate to register
> Store register
>
> Signed-off-by: Yang Shi <yang.shi@linaro.org>
> CC: Zi Shen Lim <zlim.lnx@gmail.com>

Had email exchange offline with Zi Shen Lim since he is traveling and 
cannot send text-only mail, quoted below for his reply:

"I've given reviewed-by in response to original posting. Unless 
something has changed, feel free to add it."

Since there is nothing changed, added his reviewed-by.

Reviewed-by: Zi Shen Lim <zlim.lnx@gmail.com>

Thanks,
Yang

> CC: Xi Wang <xi.wang@gmail.com>
> ---
> Thsi patch might be buried by the storm of xadd discussion, however, it is
> absolutely irrelevent to xadd, so resend the patch itself.
>
>   arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++-
>   1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
> index 6809647..49c1f1b 100644
> --- a/arch/arm64/net/bpf_jit_comp.c
> +++ b/arch/arm64/net/bpf_jit_comp.c
> @@ -563,7 +563,25 @@ emit_cond_jmp:
>   	case BPF_ST | BPF_MEM | BPF_H:
>   	case BPF_ST | BPF_MEM | BPF_B:
>   	case BPF_ST | BPF_MEM | BPF_DW:
> -		goto notyet;
> +		/* Load imm to a register then store it */
> +		ctx->tmp_used = 1;
> +		emit_a64_mov_i(1, tmp2, off, ctx);
> +		emit_a64_mov_i(1, tmp, imm, ctx);
> +		switch (BPF_SIZE(code)) {
> +		case BPF_W:
> +			emit(A64_STR32(tmp, dst, tmp2), ctx);
> +			break;
> +		case BPF_H:
> +			emit(A64_STRH(tmp, dst, tmp2), ctx);
> +			break;
> +		case BPF_B:
> +			emit(A64_STRB(tmp, dst, tmp2), ctx);
> +			break;
> +		case BPF_DW:
> +			emit(A64_STR64(tmp, dst, tmp2), ctx);
> +			break;
> +		}
> +		break;
>
>   	/* STX: *(size *)(dst + off) = src */
>   	case BPF_STX | BPF_MEM | BPF_W:
>

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#1281537

On Tue, Dec 01, 2015 at 02:20:40PM -0800, Shi, Yang wrote:
> On 11/30/2015 2:24 PM, Yang Shi wrote:
> >aarch64 doesn't have native store immediate instruction, such operation
> >has to be implemented by the below instruction sequence:
> >
> >Load immediate to register
> >Store register
> >
> >Signed-off-by: Yang Shi <yang.shi@linaro.org>
> >CC: Zi Shen Lim <zlim.lnx@gmail.com>
> 
> Had email exchange offline with Zi Shen Lim since he is traveling and cannot
> send text-only mail, quoted below for his reply:
> 
> "I've given reviewed-by in response to original posting. Unless something
> has changed, feel free to add it."
> 
> Since there is nothing changed, added his reviewed-by.
> 
> Reviewed-by: Zi Shen Lim <zlim.lnx@gmail.com>

I assume David will take this via netdev.

Will
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#1282365

From: Will Deacon <will.deacon@arm.com>
Date: Wed, 2 Dec 2015 09:15:18 +0000

> On Tue, Dec 01, 2015 at 02:20:40PM -0800, Shi, Yang wrote:
>> On 11/30/2015 2:24 PM, Yang Shi wrote:
>> >aarch64 doesn't have native store immediate instruction, such operation
>> >has to be implemented by the below instruction sequence:
>> >
>> >Load immediate to register
>> >Store register
>> >
>> >Signed-off-by: Yang Shi <yang.shi@linaro.org>
>> >CC: Zi Shen Lim <zlim.lnx@gmail.com>
>> 
>> Had email exchange offline with Zi Shen Lim since he is traveling and cannot
>> send text-only mail, quoted below for his reply:
>> 
>> "I've given reviewed-by in response to original posting. Unless something
>> has changed, feel free to add it."
>> 
>> Since there is nothing changed, added his reviewed-by.
>> 
>> Reviewed-by: Zi Shen Lim <zlim.lnx@gmail.com>
> 
> I assume David will take this via netdev.

Yes, I will, thanks.
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#1283176

From: Yang Shi <yang.shi@linaro.org>
Date: Mon, 30 Nov 2015 14:24:07 -0800

> aarch64 doesn't have native store immediate instruction, such operation
> has to be implemented by the below instruction sequence:
> 
> Load immediate to register
> Store register
> 
> Signed-off-by: Yang Shi <yang.shi@linaro.org>

Applied, thanks.
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