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| Started by | Gabriel Fernandez <gabriel.fernandez@linaro.org> |
|---|---|
| First post | 2015-09-16 09:50 +0200 |
| Last post | 2015-09-18 09:40 +0200 |
| Articles | 8 — 3 participants |
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[RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2015-09-16 09:50 +0200
[PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez <gabriel.fernandez@linaro.org> - 2015-09-16 09:50 +0200
Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Stephen Boyd <sboyd@codeaurora.org> - 2015-09-17 21:00 +0200
Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Maxime Coquelin <maxime.coquelin@st.com> - 2015-09-18 09:40 +0200
Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Stephen Boyd <sboyd@codeaurora.org> - 2015-09-17 00:40 +0200
Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Maxime Coquelin <maxime.coquelin@st.com> - 2015-09-17 11:50 +0200
Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Stephen Boyd <sboyd@codeaurora.org> - 2015-09-17 20:20 +0200
Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 Maxime Coquelin <maxime.coquelin@st.com> - 2015-09-18 09:40 +0200
| From | Gabriel Fernandez <gabriel.fernandez@linaro.org> |
|---|---|
| Date | 2015-09-16 09:50 +0200 |
| Subject | [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2 |
| Message-ID | <q9fDA-6qt-21@gated-at.bofh.it> |
This patch set fixes a kernel crash :
[ 2.433152] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.2.0-rc7-next-20150821 #134
[ 2.440713] Hardware name: STiH415/416 SoC with Flattened Device Tree
[ 2.447173] [<c00183ac>] (unwind_backtrace) from [<c0013cac>] (show_stack+0x10/0x14)
[ 2.454914] [<c0013cac>] (show_stack) from [<c0284f80>] (dump_stack+0x8c/0x9c)
[ 2.462145] [<c0284f80>] (dump_stack) from [<c0283a54>] (Ldiv0+0x8/0x10)
[ 2.468845] [<c0283a54>] (Ldiv0) from [<c0690e90>] (flexgen_round_rate+0x54/0x68)
[ 2.476327] [<c0690e90>] (flexgen_round_rate) from [<c06791f4>] (clk_calc_new_rates+0x1bc/0x22c)
[ 2.485109] [<c06791f4>] (clk_calc_new_rates) from [<c0679804>] (clk_core_set_rate_nolock+0x44/0xac)
[ 2.494235] [<c0679804>] (clk_core_set_rate_nolock) from [<c0679890>] (clk_set_rate+0x24/0x34)
[ 2.502845] [<c0679890>] (clk_set_rate) from [<c064f848>] (st_mmcss_cconfig+0x5c/0xfc)
[ 2.510763] [<c064f848>] (st_mmcss_cconfig) from [<c064fab0>] (sdhci_st_probe+0xec/0x1fc)
[ 2.518946] [<c064fab0>] (sdhci_st_probe) from [<c04334c8>] (platform_drv_probe+0x44/0xa4)
[ 2.527209] [<c04334c8>] (platform_drv_probe) from [<c0431bf4>] (driver_probe_device+0x204/0x2f0)
[ 2.536077] [<c0431bf4>] (driver_probe_device) from [<c0431d6c>] (__driver_attach+0x8c/0x90)
[ 2.544510] [<c0431d6c>] (__driver_attach) from [<c0430098>] (bus_for_each_dev+0x68/0x9c)
[ 2.552682] [<c0430098>] (bus_for_each_dev) from [<c0431320>] (bus_add_driver+0x19c/0x214)
[ 2.560941] [<c0431320>] (bus_add_driver) from [<c0432574>] (driver_register+0x78/0xf8)
[ 2.568941] [<c0432574>] (driver_register) from [<c000ab90>] (do_one_initcall+0x8c/0x1d4)
[ 2.577115] [<c000ab90>] (do_one_initcall) from [<c0b98ddc>] (kernel_init_freeable+0x158/0x1f8)
[ 2.585818] [<c0b98ddc>] (kernel_init_freeable) from [<c07b9350>] (kernel_init+0x8/0xe8)
[ 2.593905] [<c07b9350>] (kernel_init) from [<c00108a8>] (ret_from_fork+0x14/0x2c)
[ 2.601467] Division by zero in kernel.
This kernel crash is due to a broken compatibility with this commit:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
Gabriel Fernandez (2):
dt-bindings: Fix tipo in st,clkgen-pll documentation
drivers: clk: st: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 8 ++++----
drivers/clk/st/clkgen-pll.c | 12 ++++++------
3 files changed, 12 insertions(+), 12 deletions(-)
--
1.9.1
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| From | Gabriel Fernandez <gabriel.fernandez@linaro.org> |
|---|---|
| Date | 2015-09-16 09:50 +0200 |
| Subject | [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x |
| Message-ID | <q9fDB-6qt-33@gated-at.bofh.it> |
| In reply to | #1225805 |
Use a generic name for this kind of PLL
Correction in dts files are already done here:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
drivers/clk/st/clkgen-fsyn.c | 8 ++++----
drivers/clk/st/clkgen-pll.c | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 83ccf14..576cd03 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = {
},
{
.compatible = "st,stih407-quadfs660-C",
- .data = &st_fs660c32_C_407
+ .data = &st_fs660c32_C
},
{
.compatible = "st,stih407-quadfs660-D",
- .data = &st_fs660c32_D_407
+ .data = &st_fs660c32_D
},
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 47a38a9..b2a332c 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops = &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
@@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
.ops = &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
@@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = {
.data = &st_pll3200c32_407_a0,
},
{
- .compatible = "st,stih407-plls-c32-c0_0",
- .data = &st_pll3200c32_407_c0_0,
+ .compatible = "st,plls-c32-cx_0",
+ .data = &st_pll3200c32_cx_0,
},
{
- .compatible = "st,stih407-plls-c32-c0_1",
- .data = &st_pll3200c32_407_c0_1,
+ .compatible = "st,plls-c32-cx_1",
+ .data = &st_pll3200c32_cx_1,
},
{
.compatible = "st,stih407-plls-c32-a9",
--
1.9.1
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| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2015-09-17 21:00 +0200 |
| Subject | Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x |
| Message-ID | <q9Mzv-3V4-13@gated-at.bofh.it> |
| In reply to | #1225806 |
On 09/16, Gabriel Fernandez wrote:
> Use a generic name for this kind of PLL
>
> Correction in dts files are already done here:
> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
Applied to clk-fixes
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| From | Maxime Coquelin <maxime.coquelin@st.com> |
|---|---|
| Date | 2015-09-18 09:40 +0200 |
| Subject | Re: [PATCH 2/2] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x |
| Message-ID | <q9Yr0-4pF-11@gated-at.bofh.it> |
| In reply to | #1227339 |
On 09/17/2015 08:51 PM, Stephen Boyd wrote:
> On 09/16, Gabriel Fernandez wrote:
>> Use a generic name for this kind of PLL
>>
>> Correction in dts files are already done here:
>> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> ---
> Applied to clk-fixes
>
Thanks Stephen
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| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2015-09-17 00:40 +0200 |
| Message-ID | <q9twR-18J-13@gated-at.bofh.it> |
| In reply to | #1225805 |
On 09/16, Gabriel Fernandez wrote:
> This patch set fixes a kernel crash :
[..]
>
> This kernel crash is due to a broken compatibility with this commit:
> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
It isn't clear who's supposed to apply this because the To: list
is huge. Did you want to take this through arm-soc? If so, feel
free to take my acked-by on the second patch. The first patch
doesn't even apply to clk tree because the patch introducing the
typo didn't go through our tree.
--
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| From | Maxime Coquelin <maxime.coquelin@st.com> |
|---|---|
| Date | 2015-09-17 11:50 +0200 |
| Message-ID | <q9DZg-89b-31@gated-at.bofh.it> |
| In reply to | #1226547 |
On 09/17/2015 12:30 AM, Stephen Boyd wrote:
> On 09/16, Gabriel Fernandez wrote:
>> This patch set fixes a kernel crash :
> [..]
>> This kernel crash is due to a broken compatibility with this commit:
>> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
> It isn't clear who's supposed to apply this because the To: list
> is huge. Did you want to take this through arm-soc? If so, feel
> free to take my acked-by on the second patch. The first patch
> doesn't even apply to clk tree because the patch introducing the
> typo didn't go through our tree.
Indeed Stephen, I see it went through my tree (STi DT).
So the first patch should be taken through arm-soc.
The second patch, should be taken through yours I think.
Regards,
Maxime
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| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2015-09-17 20:20 +0200 |
| Message-ID | <q9LWP-38s-41@gated-at.bofh.it> |
| In reply to | #1226819 |
On 09/17, Maxime Coquelin wrote:
>
>
> On 09/17/2015 12:30 AM, Stephen Boyd wrote:
> >On 09/16, Gabriel Fernandez wrote:
> >>This patch set fixes a kernel crash :
> >[..]
> >>This kernel crash is due to a broken compatibility with this commit:
> >>commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
> >It isn't clear who's supposed to apply this because the To: list
> >is huge. Did you want to take this through arm-soc? If so, feel
> >free to take my acked-by on the second patch. The first patch
> >doesn't even apply to clk tree because the patch introducing the
> >typo didn't go through our tree.
> Indeed Stephen, I see it went through my tree (STi DT).
> So the first patch should be taken through arm-soc.
> The second patch, should be taken through yours I think.
>
Ok. That probably breaks bisectability, but if you're not
worried, I'm not worried.
--
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| From | Maxime Coquelin <maxime.coquelin@st.com> |
|---|---|
| Date | 2015-09-18 09:40 +0200 |
| Message-ID | <q9YqZ-4pF-7@gated-at.bofh.it> |
| In reply to | #1227291 |
On 09/17/2015 08:14 PM, Stephen Boyd wrote:
> On 09/17, Maxime Coquelin wrote:
>>
>> On 09/17/2015 12:30 AM, Stephen Boyd wrote:
>>> On 09/16, Gabriel Fernandez wrote:
>>>> This patch set fixes a kernel crash :
>>> [..]
>>>> This kernel crash is due to a broken compatibility with this commit:
>>>> commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")
>>> It isn't clear who's supposed to apply this because the To: list
>>> is huge. Did you want to take this through arm-soc? If so, feel
>>> free to take my acked-by on the second patch. The first patch
>>> doesn't even apply to clk tree because the patch introducing the
>>> typo didn't go through our tree.
>> Indeed Stephen, I see it went through my tree (STi DT).
>> So the first patch should be taken through arm-soc.
>> The second patch, should be taken through yours I think.
>>
> Ok. That probably breaks bisectability, but if you're not
> worried, I'm not worried.
I'm not worried about bisectability indeed, as the first patch is just
typo fixes in DT Bindings documentation.
Regards,
Maxime
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