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| Started by | Willy Tarreau <w@1wt.eu> |
|---|---|
| First post | 2015-09-13 01:20 +0200 |
| Last post | 2015-09-15 09:50 +0200 |
| Articles | 3 — 2 participants |
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[PATCH 2.6.32 35/62] MIPS: Fix cpu_has_mips_r2_exec_hazard. Willy Tarreau <w@1wt.eu> - 2015-09-13 01:20 +0200
Re: [PATCH 2.6.32 35/62] MIPS: Fix cpu_has_mips_r2_exec_hazard. Ben Hutchings <ben@decadent.org.uk> - 2015-09-15 05:10 +0200
Re: [PATCH 2.6.32 35/62] MIPS: Fix cpu_has_mips_r2_exec_hazard. Willy Tarreau <w@1wt.eu> - 2015-09-15 09:50 +0200
| From | Willy Tarreau <w@1wt.eu> |
|---|---|
| Date | 2015-09-13 01:20 +0200 |
| Subject | [PATCH 2.6.32 35/62] MIPS: Fix cpu_has_mips_r2_exec_hazard. |
| Message-ID | <q82fo-6Lq-15@gated-at.bofh.it> |
2.6.32-longterm review patch. If anyone has any objections, please let me know.
------------------
From: Ralf Baechle <ralf@linux-mips.org>
commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
Returns a non-zero value if the current processor implementation requires
an IHB instruction to deal with an instruction hazard as per MIPS R2
architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[bwh: Backported to 3.2: trim the CPU type list]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
(cherry picked from commit 8feb2a714b3478b2cde5c576fd9f47ef44b60e8d)
Signed-off-by: Willy Tarreau <w@1wt.eu>
---
arch/mips/include/asm/cpu-features.h | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1f4df64..a3dbb59 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -150,8 +150,32 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2)
+/*
+ * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
+ *
+ * Returns non-zero value if the current processor implementation requires
+ * an IHB instruction to deal with an instruction hazard as per MIPS R2
+ * architecture specification, zero otherwise.
+ */
#ifndef cpu_has_mips_r2_exec_hazard
-#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
+#define cpu_has_mips_r2_exec_hazard \
+({ \
+ int __res; \
+ \
+ switch (current_cpu_type()) { \
+ case CPU_74K: \
+ case CPU_CAVIUM_OCTEON: \
+ case CPU_CAVIUM_OCTEON_PLUS: \
+ case CPU_CAVIUM_OCTEON2: \
+ __res = 0; \
+ break; \
+ \
+ default: \
+ __res = 1; \
+ } \
+ \
+ __res; \
+})
#endif
/*
--
1.7.12.2.21.g234cd45.dirty
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| From | Ben Hutchings <ben@decadent.org.uk> |
|---|---|
| Date | 2015-09-15 05:10 +0200 |
| Message-ID | <q8ON4-GN-9@gated-at.bofh.it> |
| In reply to | #1223475 |
On Sun, 2015-09-13 at 00:56 +0200, Willy Tarreau wrote:
> 2.6.32-longterm review patch. If anyone has any objections, please let me know.
>
> ------------------
>
> From: Ralf Baechle <ralf@linux-mips.org>
>
> commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
>
> Returns a non-zero value if the current processor implementation requires
> an IHB instruction to deal with an instruction hazard as per MIPS R2
> architecture specification, zero otherwise.
>
> For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
>
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> [bwh: Backported to 3.2: trim the CPU type list]
> Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
> (cherry picked from commit 8feb2a714b3478b2cde5c576fd9f47ef44b60e8d)
>
> Signed-off-by: Willy Tarreau <w@1wt.eu>
> ---
> arch/mips/include/asm/cpu-features.h | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> index 1f4df64..a3dbb59 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -150,8 +150,32 @@
> #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
> cpu_has_mips64r1 | cpu_has_mips64r2)
>
> +/*
> + * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
> + *
> + * Returns non-zero value if the current processor implementation requires
> + * an IHB instruction to deal with an instruction hazard as per MIPS R2
> + * architecture specification, zero otherwise.
> + */
> #ifndef cpu_has_mips_r2_exec_hazard
> -#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
> +#define cpu_has_mips_r2_exec_hazard \
> +({ \
> + int __res; \
> + \
> + switch (current_cpu_type()) { \
> + case CPU_74K: \
> + case CPU_CAVIUM_OCTEON: \
> + case CPU_CAVIUM_OCTEON_PLUS: \
> + case CPU_CAVIUM_OCTEON2: \
[...]
These last two constants aren't defined in 2.6.32, so they would need to
be removed too. But I don't think this is needed at all.
Ben.
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| From | Willy Tarreau <w@1wt.eu> |
|---|---|
| Date | 2015-09-15 09:50 +0200 |
| Message-ID | <q8Ta2-6M4-11@gated-at.bofh.it> |
| In reply to | #1224615 |
On Tue, Sep 15, 2015 at 04:02:25AM +0100, Ben Hutchings wrote:
> On Sun, 2015-09-13 at 00:56 +0200, Willy Tarreau wrote:
> > 2.6.32-longterm review patch. If anyone has any objections, please let me know.
> >
> > ------------------
> >
> > From: Ralf Baechle <ralf@linux-mips.org>
> >
> > commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
> >
> > Returns a non-zero value if the current processor implementation requires
> > an IHB instruction to deal with an instruction hazard as per MIPS R2
> > architecture specification, zero otherwise.
> >
> > For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
> >
> > Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> > [bwh: Backported to 3.2: trim the CPU type list]
> > Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
> > (cherry picked from commit 8feb2a714b3478b2cde5c576fd9f47ef44b60e8d)
> >
> > Signed-off-by: Willy Tarreau <w@1wt.eu>
> > ---
> > arch/mips/include/asm/cpu-features.h | 26 +++++++++++++++++++++++++-
> > 1 file changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> > index 1f4df64..a3dbb59 100644
> > --- a/arch/mips/include/asm/cpu-features.h
> > +++ b/arch/mips/include/asm/cpu-features.h
> > @@ -150,8 +150,32 @@
> > #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
> > cpu_has_mips64r1 | cpu_has_mips64r2)
> >
> > +/*
> > + * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
> > + *
> > + * Returns non-zero value if the current processor implementation requires
> > + * an IHB instruction to deal with an instruction hazard as per MIPS R2
> > + * architecture specification, zero otherwise.
> > + */
> > #ifndef cpu_has_mips_r2_exec_hazard
> > -#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
> > +#define cpu_has_mips_r2_exec_hazard \
> > +({ \
> > + int __res; \
> > + \
> > + switch (current_cpu_type()) { \
> > + case CPU_74K: \
> > + case CPU_CAVIUM_OCTEON: \
> > + case CPU_CAVIUM_OCTEON_PLUS: \
> > + case CPU_CAVIUM_OCTEON2: \
> [...]
>
> These last two constants aren't defined in 2.6.32, so they would need to
> be removed too. But I don't think this is needed at all.
Ah thanks, I only built x86_64 and i386. OK I'm dropping the whole patch.
Thanks,
Willy
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