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[PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND

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  [PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND Alban Bedel <albeu@free.fr> - 2015-09-01 17:30 +0200
    Re: [PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND Arnd Bergmann <arnd@arndb.de> - 2015-09-07 15:30 +0200
      Re: [PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND Alban <albeu@free.fr> - 2015-09-09 16:20 +0200
        Re: [PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND Arnd Bergmann <arnd@arndb.de> - 2015-09-09 16:30 +0200

#1216932 — [PATCH 0/4] MIPS: ath79: Add USB support on the TL-WR1043ND

Hi,

this serie add a driver for the USB phy on the ATH79 SoCs and enable the
USB port on the TL-WR1043ND. The phy controller is really trivial as it
only use reset lines.

Alban

Alban Bedel (4):
  devicetree: Add bindings for the ATH79 USB phy
  phy: Add a driver for the ATH79 USB phy
  MIPS: ath79: Add the EHCI controller and USB phy to the AR9132 dtsi
  MIPS: ath79: Enable the USB port on the TL-WR1043ND

 .../devicetree/bindings/phy/phy-ath79-usb.txt      |  18 ++++
 arch/mips/boot/dts/qca/ar9132.dtsi                 |  24 +++++
 arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts   |   4 +
 drivers/phy/Kconfig                                |   8 ++
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-ath79-usb.c                        | 115 +++++++++++++++++++++
 6 files changed, 170 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
 create mode 100644 drivers/phy/phy-ath79-usb.c

-- 
2.0.0

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#1220174

On Tuesday 01 September 2015 17:23:10 Alban Bedel wrote:
> 
> this serie add a driver for the USB phy on the ATH79 SoCs and enable the
> USB port on the TL-WR1043ND. The phy controller is really trivial as it
> only use reset lines.
> 

Is this a common thing to have? If other PHY devices are like this, we
could instead add a simple generic PHY driver that just asserts all
its reset lines in the order as provided, rather than making this a
hardware specific driver that ends up getting copied several times.

	Arnd
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#1221491

On Mon, 07 Sep 2015 15:20:42 +0200
Arnd Bergmann <arnd@arndb.de> wrote:

> On Tuesday 01 September 2015 17:23:10 Alban Bedel wrote:
> > 
> > this serie add a driver for the USB phy on the ATH79 SoCs and enable the
> > USB port on the TL-WR1043ND. The phy controller is really trivial as it
> > only use reset lines.
> > 
> 
> Is this a common thing to have? If other PHY devices are like this, we
> could instead add a simple generic PHY driver that just asserts all
> its reset lines in the order as provided, rather than making this a
> hardware specific driver that ends up getting copied several times.

I don't know how common it is. However I agree that a simple driver that
can start a clock and toggle a few GPIO and/or reset would make sense.

However in the case of the ATH79 SoC some models have a reset line that
is misused to force the PHY in sleep mode. Sadly this extra reset must
be asserted for the PHY to work, so it wouldn't fit in such a generic
design.

Still we could have such a generic driver and let the ATH79 driver
build on top of it. Honestly that's what I wanted to do, but getting
generic drivers with DT support accepted is not easy. That's why I went
with this driver, it is technically inferior but much easier to get
considered for merging.

Alban
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#1221494

On Wednesday 09 September 2015 16:14:59 Alban wrote:
> On Mon, 07 Sep 2015 15:20:42 +0200
> Arnd Bergmann <arnd@arndb.de> wrote:
> 
> > On Tuesday 01 September 2015 17:23:10 Alban Bedel wrote:
> > > 
> > > this serie add a driver for the USB phy on the ATH79 SoCs and enable the
> > > USB port on the TL-WR1043ND. The phy controller is really trivial as it
> > > only use reset lines.
> > > 
> > 
> > Is this a common thing to have? If other PHY devices are like this, we
> > could instead add a simple generic PHY driver that just asserts all
> > its reset lines in the order as provided, rather than making this a
> > hardware specific driver that ends up getting copied several times.
> 
> I don't know how common it is. However I agree that a simple driver that
> can start a clock and toggle a few GPIO and/or reset would make sense.
> 
> However in the case of the ATH79 SoC some models have a reset line that
> is misused to force the PHY in sleep mode. Sadly this extra reset must
> be asserted for the PHY to work, so it wouldn't fit in such a generic
> design.
> 
> Still we could have such a generic driver and let the ATH79 driver
> build on top of it. Honestly that's what I wanted to do, but getting
> generic drivers with DT support accepted is not easy. That's why I went
> with this driver, it is technically inferior but much easier to get
> considered for merging.

Ok, fair enough. If we end up doing a more generic driver for this,
we can still consider adding the compatible string there, potentially
with some workaround for the sleep mode.

	Arnd
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