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[PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller

Started byVaibhav Hiremath <vaibhav.hiremath@linaro.org>
First post2015-09-04 17:40 +0200
Last post2015-09-07 12:40 +0200
Articles 5 — 1 participant

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  [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath <vaibhav.hiremath@linaro.org> - 2015-09-04 17:40 +0200
    [PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support Vaibhav Hiremath <vaibhav.hiremath@linaro.org> - 2015-09-04 17:40 +0200
    [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock Vaibhav Hiremath <vaibhav.hiremath@linaro.org> - 2015-09-04 17:40 +0200
    [PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields Vaibhav Hiremath <vaibhav.hiremath@linaro.org> - 2015-09-04 17:40 +0200
    Re: [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI  controller Vaibhav Hiremath <vaibhav.hiremath@linaro.org> - 2015-09-07 12:40 +0200

#1219125 — [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller

FromVaibhav Hiremath <vaibhav.hiremath@linaro.org>
Date2015-09-04 17:40 +0200
Subject[PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller
Message-ID<q51fP-6d7-13@gated-at.bofh.it>
PXA1928 SDHCI controller has few differences, for example,

                           PXAxxx                    PXA1928
                           ======                    =======
   SDCLK_DELAY field       0x10A                     0x114
   SDCLK_DELAY mask        0x1F                      0x3FF
   SDCLK_DELAY shift        9                          8
   SDCLK_SEL shift          8                          2 (SEL1)

So this patch series introduces new compatible device_id
(marvell,pxav3-1928-sdhci), and makes use of .data for handling
such differences.

The series also adds support like,

 - independent ->set_clock() api, as we need to enable internal clock gate
    and TX clock
 - pinctrl configuration based on bus speed.
 - introduce new quirk SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER
   SD_BUS_POWER & SD_BUS_VLT bit-fields are used internally to gate the
   clocks, so it is important to configure them as part of ->set_power()
   More detailed description is written into commit log.
 - Enable SDHCI_QUIRK_BROKEN_TIMEOUT_VAL for PXA1928 device_id


Testing:
I have done basic testing on both eMMC and SD card on PXA1928 based
platform.

Note: I tried to made sure that I do not break any other platform, which
used sdhci, except HS200 configuration. 
Unfortunately I do not have access to any other datasheets, where I can
cross check the details on HS200 bit-fields. Probably someone who has
access can confirm [PATCH 4/5], whether it impacts other platforms.

Kevin Liu (1):
  mmc: sdhci-pxav3: Fix HS200 mode support

Vaibhav Hiremath (4):
  mmc: sdhci-pxav3: Enable pxa1928 device support
  mmc: sdhci-pxav3: Add platform specific set_clock ops
  mmc: sdhci-pxav3: Add pinctl setting according to bus clock
  mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields

 drivers/mmc/host/sdhci-pltfm.c |   3 +
 drivers/mmc/host/sdhci-pxav3.c | 168 ++++++++++++++++++++++++++++++++++++++---
 drivers/mmc/host/sdhci.c       |   3 +-
 drivers/mmc/host/sdhci.h       |   2 +
 4 files changed, 163 insertions(+), 13 deletions(-)

-- 
1.9.1

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#1219126 — [PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support

FromVaibhav Hiremath <vaibhav.hiremath@linaro.org>
Date2015-09-04 17:40 +0200
Subject[PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support
Message-ID<q51fQ-6d7-19@gated-at.bofh.it>
In reply to#1219125
From: Kevin Liu <kliu5@marvell.com>

IN case of MMC HS200 mode, current code does not enable
SD_CE_ATA_2.MMC_HS200 & SD_CE_ATA_2.MMC_CARD bit configurations.

So this patch updates the above bit fields correctly.

Signed-off-by: Tim Wang <wangtt@marvell.com>
Signed-off-by: Kevin Liu <kliu5@marvell.com>
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
---
Note: Unfortunately I do not have access to any other datasheets
which uses sdhci-pxav3 driver, so quite not sure whether this would
break any existing platform, probably NOT, as I do not see any
references for this change.
If anyone can confirm that would be really great.

 drivers/mmc/host/sdhci-pxav3.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index d933f75..6978810 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -57,6 +57,8 @@
 #define SD_CE_ATA_1			0x10C
 
 #define SD_CE_ATA_2			0x10E
+#define  SD_CE_ATA2_HS200_EN		BIT(10)
+#define  SD_CE_ATA2_MMC_MODE		BIT(12)
 #define  SDCE_MISC_INT			BIT(2)
 #define  SDCE_MISC_INT_EN		BIT(1)
 
@@ -330,6 +332,17 @@ static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs)
 	return pinctrl_select_state(pxa->pinctrl, pinctrl);
 }
 
+static int pxav3_select_hs200(struct sdhci_host *host)
+{
+	u16 reg = 0;
+
+	reg = sdhci_readw(host, SD_CE_ATA_2);
+	reg |= SD_CE_ATA2_HS200_EN | SD_CE_ATA2_MMC_MODE;
+	sdhci_writew(host, reg, SD_CE_ATA_2);
+
+	return 0;
+}
+
 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -361,6 +374,10 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 	case MMC_TIMING_UHS_DDR50:
 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 		break;
+	case MMC_TIMING_MMC_HS200:
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+		pxav3_select_hs200(host);
+		break;
 	}
 
 	/*
-- 
1.9.1

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#1219127 — [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock

FromVaibhav Hiremath <vaibhav.hiremath@linaro.org>
Date2015-09-04 17:40 +0200
Subject[PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock
Message-ID<q51fQ-6d7-21@gated-at.bofh.it>
In reply to#1219125
Different bus clock may need different pin setting.
For example, fast bus clock like 208Mhz need pin drive fast
while slow bus clock prefer pin drive slow to guarantee
signal quality.

So this patch creates two states,
  - Default (slow/normal) pin state
  - And fast pin state for higher freq bus speed.

And selection of pin state is done based on timing mode.

Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Kevin Liu <kliu5@marvell.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 45 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index c2b2b78..d933f75 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -35,6 +35,7 @@
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
 #include <linux/mbus.h>
+#include <linux/pinctrl/consumer.h>
 
 #include "sdhci.h"
 #include "sdhci-pltfm.h"
@@ -92,6 +93,10 @@ struct sdhci_pxa {
 	void __iomem *io_pwr_reg;
 	void __iomem *io_pwr_lock_reg;
 	struct sdhci_pxa_data *data;
+
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *pins_default;
+	struct pinctrl_state *pins_fast;
 };
 
 static struct sdhci_pxa_data pxav3_data_v1 = {
@@ -298,6 +303,33 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 	pxa->power_mode = power_mode;
 }
 
+static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_pxa *pxa = pltfm_host->priv;
+	struct pinctrl_state *pinctrl;
+
+	if (IS_ERR(pxa->pinctrl) ||
+		IS_ERR(pxa->pins_default) ||
+		IS_ERR(pxa->pins_fast))
+		return -EINVAL;
+
+	switch (uhs) {
+	case MMC_TIMING_UHS_SDR50:
+	case MMC_TIMING_UHS_SDR104:
+	case MMC_TIMING_MMC_HS200:
+	case MMC_TIMING_MMC_HS400:
+		pinctrl = pxa->pins_fast;
+		break;
+	default:
+		/* back to default state for other legacy timing */
+		pinctrl = pxa->pins_default;
+		break;
+	}
+
+	return pinctrl_select_state(pxa->pinctrl, pinctrl);
+}
+
 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -353,6 +385,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 	dev_dbg(mmc_dev(host->mmc),
 		"%s uhs = %d, ctrl_2 = %04X\n",
 		__func__, uhs, ctrl_2);
+
+	pxav3_select_pinstate(host, uhs);
 }
 
 static void pxav3_voltage_switch(struct sdhci_host *host,
@@ -416,7 +450,6 @@ static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock)
 		/* TX internal clock selection */
 		pxav3_set_tx_clock(host);
 	}
-
 }
 
 static const struct sdhci_ops pxav3_sdhci_ops = {
@@ -586,6 +619,16 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		}
 	}
 
+	pxa->pinctrl = devm_pinctrl_get(dev);
+	if (!IS_ERR(pxa->pinctrl)) {
+		pxa->pins_default = pinctrl_lookup_state(pxa->pinctrl, "default");
+		if (IS_ERR(pxa->pins_default))
+			dev_err(dev, "could not get default pinstate\n");
+		pxa->pins_fast = pinctrl_lookup_state(pxa->pinctrl, "fast");
+		if (IS_ERR(pxa->pins_fast))
+			dev_info(dev, "could not get fast pinstate\n");
+	}
+
 	pm_runtime_get_noresume(&pdev->dev);
 	pm_runtime_set_active(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
-- 
1.9.1

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#1219128 — [PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields

FromVaibhav Hiremath <vaibhav.hiremath@linaro.org>
Date2015-09-04 17:40 +0200
Subject[PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields
Message-ID<q51fQ-6d7-31@gated-at.bofh.it>
In reply to#1219125
IN case of Marvell 1928 family of devices, the SD_BUS_POWER and
SD_BUS_VLT bits are used internally to gate the clocks, so
we have to set these fields.

Pasting Spec words here,

The <SD_BUS_VLT> and <SD_BUS_POWER> fields should be configured
to correct values. These actually do not do the voltage selection
or switch power to the SD card. However these fields are used
internally to gate the clock. So if these fields are set
incorrectly, SD module will not function.

And during my development, I have seen that SD card wouldn't function
without right configuration into these fields.

So this patch adds new quirk (SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER),
which make sure that ->set_power() sets these fields.

Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
---
 drivers/mmc/host/sdhci-pltfm.c | 3 +++
 drivers/mmc/host/sdhci.c       | 3 ++-
 drivers/mmc/host/sdhci.h       | 2 ++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index a207f5a..0872da0 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -101,6 +101,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
 	    of_device_is_compatible(np, "fsl,mpc8536-esdhc"))
 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
+	if (of_device_is_compatible(np, "marvell,pxav3-988-sdhci"))
+		host->quirks2 |= SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER;
+
 	clk = of_get_property(np, "clock-frequency", &size);
 	if (clk && size == sizeof(*clk) && *clk)
 		pltfm_host->clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 2d58b31..418f381 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1265,7 +1265,8 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
 		else
 			sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 
-		return;
+		if (!(host->quirks2 | SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER))
+			return;
 	}
 
 	if (mode != MMC_POWER_OFF) {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 9b0e2a8..8802a0c 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -409,6 +409,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_SUPPORT_SINGLE			(1<<13)
 /* Controller broken with using ACMD23 */
 #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
+/* Voltage capabilities of Controller must be set  */
+#define SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER		(1<<15)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.9.1

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#1220043 — Re: [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller

FromVaibhav Hiremath <vaibhav.hiremath@linaro.org>
Date2015-09-07 12:40 +0200
SubjectRe: [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller
Message-ID<q620a-2XP-3@gated-at.bofh.it>
In reply to#1219125

On Friday 04 September 2015 09:02 PM, Vaibhav Hiremath wrote:
> PXA1928 SDHCI controller has few differences, for example,
>
>                             PXAxxx                    PXA1928
>                             ======                    =======
>     SDCLK_DELAY field       0x10A                     0x114
>     SDCLK_DELAY mask        0x1F                      0x3FF
>     SDCLK_DELAY shift        9                          8
>     SDCLK_SEL shift          8                          2 (SEL1)
>
> So this patch series introduces new compatible device_id
> (marvell,pxav3-1928-sdhci), and makes use of .data for handling
> such differences.
>
> The series also adds support like,
>
>   - independent ->set_clock() api, as we need to enable internal clock gate
>      and TX clock
>   - pinctrl configuration based on bus speed.
>   - introduce new quirk SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER
>     SD_BUS_POWER & SD_BUS_VLT bit-fields are used internally to gate the
>     clocks, so it is important to configure them as part of ->set_power()
>     More detailed description is written into commit log.
>   - Enable SDHCI_QUIRK_BROKEN_TIMEOUT_VAL for PXA1928 device_id
>

Please ignore this series, as one residual change (rather typo error).
Mistakenly while checking in the code, instead of 1928 compatible
property it was 988.

I will submit the new series shortly.

Thanks,
Vaibhav


>
> Testing:
> I have done basic testing on both eMMC and SD card on PXA1928 based
> platform.
>
> Note: I tried to made sure that I do not break any other platform, which
> used sdhci, except HS200 configuration.
> Unfortunately I do not have access to any other datasheets, where I can
> cross check the details on HS200 bit-fields. Probably someone who has
> access can confirm [PATCH 4/5], whether it impacts other platforms.
>
> Kevin Liu (1):
>    mmc: sdhci-pxav3: Fix HS200 mode support
>
> Vaibhav Hiremath (4):
>    mmc: sdhci-pxav3: Enable pxa1928 device support
>    mmc: sdhci-pxav3: Add platform specific set_clock ops
>    mmc: sdhci-pxav3: Add pinctl setting according to bus clock
>    mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields
>
>   drivers/mmc/host/sdhci-pltfm.c |   3 +
>   drivers/mmc/host/sdhci-pxav3.c | 168 ++++++++++++++++++++++++++++++++++++++---
>   drivers/mmc/host/sdhci.c       |   3 +-
>   drivers/mmc/host/sdhci.h       |   2 +
>   4 files changed, 163 insertions(+), 13 deletions(-)
>
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