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[PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600

Started byChristophe Leroy <christophe.leroy@c-s.fr>
First post2015-09-03 11:30 +0200
Last post2015-09-04 22:00 +0200
Articles 6 — 5 participants

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  [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600 Christophe Leroy <christophe.leroy@c-s.fr> - 2015-09-03 11:30 +0200
    Re: [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600 Michael Ellerman <mpe@ellerman.id.au> - 2015-09-03 11:50 +0200
    Re: [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600 Scott Wood <scottwood@freescale.com> - 2015-09-04 18:50 +0200
      Re: [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600 christophe leroy <christophe.leroy@c-s.fr> - 2015-09-04 20:10 +0200
        Re: [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600 Segher Boessenkool <segher@kernel.crashing.org> - 2015-09-04 21:00 +0200
        Re: [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600 Segher Boessenkool <segher@kernel.crashing.org> - 2015-09-04 22:00 +0200

#1218125 — [PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600

FromChristophe Leroy <christophe.leroy@c-s.fr>
Date2015-09-03 11:30 +0200
Subject[PATCH] powerpc/book3s32: Only select PPC_HAVE_PMU on e600
Message-ID<q4z0e-7Rx-21@gated-at.bofh.it>
On PPC832x, perf record/report reports martian addresses

     2.62%  perf_reseau4  libpthread-2.18.so  [.] __libc_send
     2.56%  perf_reseau4  [kernel.kallsyms]   [k] __ip_make_skb
     1.62%  perf_reseau4  [kernel.kallsyms]   [k] __ip_append_data.isra.39
     1.55%  perf_reseau4  [kernel.kallsyms]   [k] ip_finish_output
     1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd94
     1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd95
     1.28%  perf_reseau4  [unknown]           [k] 0x7ffffd97
     1.26%  perf_reseau4  [unknown]           [k] 0x7ffffda3
     1.24%  perf_reseau4  [unknown]           [k] 0x7ffffd98
     1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd92
     1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd9b
     [.....]

This is due to function perf_instruction_pointer() reading SPR SIAR
which doesn't exist on e300 core. The perf_instruction_pointer() is
redefined in arch/powerpc/perf/core-book3s.c when CONFIG_PPC_PERF_CTRS
is selected.

This patch moves the selection of CONFIG_PPC_HAVE_PMU in 86xx section
so that CONFIG_PPC_PERF_CTRS won't be selected for other 6xx powerpc

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
 arch/powerpc/platforms/86xx/Kconfig    | 1 +
 arch/powerpc/platforms/Kconfig.cputype | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 1afd1e4..bb24d2a 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -5,6 +5,7 @@ menuconfig PPC_86xx
 	select FSL_SOC
 	select ALTIVEC
 	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select PPC_HAVE_PMU_SUPPORT
 	help
 	  The Freescale E600 SoCs have 74xx cores.
 
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index d642cf9..aa63b12 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -143,7 +143,6 @@ config PPC_BOOK3E
 config 6xx
 	def_bool y
 	depends on PPC32 && PPC_BOOK3S
-	select PPC_HAVE_PMU_SUPPORT
 
 config TUNE_CELL
 	bool "Optimize for Cell Broadband Engine"
-- 
2.1.0

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#1218132

FromMichael Ellerman <mpe@ellerman.id.au>
Date2015-09-03 11:50 +0200
Message-ID<q4zjz-8gK-9@gated-at.bofh.it>
In reply to#1218125
On Thu, 2015-09-03 at 11:27 +0200, Christophe Leroy wrote:
> On PPC832x, perf record/report reports martian addresses
> 
>      2.62%  perf_reseau4  libpthread-2.18.so  [.] __libc_send
>      2.56%  perf_reseau4  [kernel.kallsyms]   [k] __ip_make_skb
>      1.62%  perf_reseau4  [kernel.kallsyms]   [k] __ip_append_data.isra.39
>      1.55%  perf_reseau4  [kernel.kallsyms]   [k] ip_finish_output
>      1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd94
>      1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd95
>      1.28%  perf_reseau4  [unknown]           [k] 0x7ffffd97
>      1.26%  perf_reseau4  [unknown]           [k] 0x7ffffda3
>      1.24%  perf_reseau4  [unknown]           [k] 0x7ffffd98
>      1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd92
>      1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd9b
>      [.....]
> 
> This is due to function perf_instruction_pointer() reading SPR SIAR
> which doesn't exist on e300 core. The perf_instruction_pointer() is
> redefined in arch/powerpc/perf/core-book3s.c when CONFIG_PPC_PERF_CTRS
> is selected.
> 
> This patch moves the selection of CONFIG_PPC_HAVE_PMU in 86xx section
> so that CONFIG_PPC_PERF_CTRS won't be selected for other 6xx powerpc

I don't know much about these old 6xx cpus, deferring to Paul.

cheers


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#1219166

FromScott Wood <scottwood@freescale.com>
Date2015-09-04 18:50 +0200
Message-ID<q52lB-7Jv-27@gated-at.bofh.it>
In reply to#1218125
On Thu, Sep 03, 2015 at 11:27:03AM +0200, Christophe Leroy wrote:
> On PPC832x, perf record/report reports martian addresses
> 
>      2.62%  perf_reseau4  libpthread-2.18.so  [.] __libc_send
>      2.56%  perf_reseau4  [kernel.kallsyms]   [k] __ip_make_skb
>      1.62%  perf_reseau4  [kernel.kallsyms]   [k] __ip_append_data.isra.39
>      1.55%  perf_reseau4  [kernel.kallsyms]   [k] ip_finish_output
>      1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd94
>      1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd95
>      1.28%  perf_reseau4  [unknown]           [k] 0x7ffffd97
>      1.26%  perf_reseau4  [unknown]           [k] 0x7ffffda3
>      1.24%  perf_reseau4  [unknown]           [k] 0x7ffffd98
>      1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd92
>      1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd9b
>      [.....]
> 
> This is due to function perf_instruction_pointer() reading SPR SIAR
> which doesn't exist on e300 core. The perf_instruction_pointer() is
> redefined in arch/powerpc/perf/core-book3s.c when CONFIG_PPC_PERF_CTRS
> is selected.
> 
> This patch moves the selection of CONFIG_PPC_HAVE_PMU in 86xx section
> so that CONFIG_PPC_PERF_CTRS won't be selected for other 6xx powerpc
> 
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

So, what happens when a kernel is built that supports both 83xx and 86xx? 
Plus, it's e300, not e600, that is the exception among 6xx-style cores.

-Scott
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#1219229

Fromchristophe leroy <christophe.leroy@c-s.fr>
Date2015-09-04 20:10 +0200
Message-ID<q53AZ-1e2-9@gated-at.bofh.it>
In reply to#1219166

Le 04/09/2015 18:43, Scott Wood a écrit :
> On Thu, Sep 03, 2015 at 11:27:03AM +0200, Christophe Leroy wrote:
>> On PPC832x, perf record/report reports martian addresses
>>
>>       2.62%  perf_reseau4  libpthread-2.18.so  [.] __libc_send
>>       2.56%  perf_reseau4  [kernel.kallsyms]   [k] __ip_make_skb
>>       1.62%  perf_reseau4  [kernel.kallsyms]   [k] __ip_append_data.isra.39
>>       1.55%  perf_reseau4  [kernel.kallsyms]   [k] ip_finish_output
>>       1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd94
>>       1.33%  perf_reseau4  [unknown]           [k] 0x7ffffd95
>>       1.28%  perf_reseau4  [unknown]           [k] 0x7ffffd97
>>       1.26%  perf_reseau4  [unknown]           [k] 0x7ffffda3
>>       1.24%  perf_reseau4  [unknown]           [k] 0x7ffffd98
>>       1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd92
>>       1.22%  perf_reseau4  [unknown]           [k] 0x7ffffd9b
>>       [.....]
>>
>> This is due to function perf_instruction_pointer() reading SPR SIAR
>> which doesn't exist on e300 core. The perf_instruction_pointer() is
>> redefined in arch/powerpc/perf/core-book3s.c when CONFIG_PPC_PERF_CTRS
>> is selected.
>>
>> This patch moves the selection of CONFIG_PPC_HAVE_PMU in 86xx section
>> so that CONFIG_PPC_PERF_CTRS won't be selected for other 6xx powerpc
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> So, what happens when a kernel is built that supports both 83xx and 86xx?
Right, so should we define a processor feature for it ?
> Plus, it's e300, not e600, that is the exception among 6xx-style cores.
Is it ? I've been looking for special register SIAR (spr 955) in several 
6xx reference manuals.
82xx doesn't have it, 52xx and 512x don't have it.
I found it only in the 86xx
Which other family has it ?

Christophe

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#1219251

FromSegher Boessenkool <segher@kernel.crashing.org>
Date2015-09-04 21:00 +0200
Message-ID<q54no-286-5@gated-at.bofh.it>
In reply to#1219229
On Fri, Sep 04, 2015 at 08:00:59PM +0200, christophe leroy wrote:
> >Plus, it's e300, not e600, that is the exception among 6xx-style cores.
> Is it ? I've been looking for special register SIAR (spr 955) in several 
> 6xx reference manuals.
> 82xx doesn't have it, 52xx and 512x don't have it.
> I found it only in the 86xx
> Which other family has it ?

7xx, 7xxx have it.  I don't think any 603 or 604 have it.


Segher
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#1219277

FromSegher Boessenkool <segher@kernel.crashing.org>
Date2015-09-04 22:00 +0200
Message-ID<q55js-3sI-3@gated-at.bofh.it>
In reply to#1219229
[ it seems my previous mail disappeared down the void ]

On Fri, Sep 04, 2015 at 08:00:59PM +0200, christophe leroy wrote:
> >Plus, it's e300, not e600, that is the exception among 6xx-style cores.
> Is it ? I've been looking for special register SIAR (spr 955) in several 
> 6xx reference manuals.
> 82xx doesn't have it, 52xx and 512x don't have it.
> I found it only in the 86xx
> Which other family has it ?

All 7xx and 7xxx have it.  No 603 or 604 does afaik.


Segher
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