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Groups > linux.kernel > #1216602 > unrolled thread
| Started by | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| First post | 2015-09-01 07:50 +0200 |
| Last post | 2015-09-07 04:30 +0200 |
| Articles | 20 on this page of 71 — 8 participants |
Back to article view | Back to linux.kernel
[PATCH v4 0/16] Add Analogix Core Display Port Driver Yakir Yang <ykk@rock-chips.com> - 2015-09-01 07:50 +0200
[PATCH v4 01/16] drm: exynos/dp: fix code style Yakir Yang <ykk@rock-chips.com> - 2015-09-01 07:50 +0200
Re: [PATCH v4 01/16] drm: exynos/dp: fix code style Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-03 02:30 +0200
Re: [PATCH v4 01/16] drm: exynos/dp: fix code style Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-03 07:10 +0200
Re: [PATCH v4 01/16] drm: exynos/dp: fix code style Yakir Yang <ykk@rock-chips.com> - 2015-09-03 07:40 +0200
Re: [PATCH v4 01/16] drm: exynos/dp: fix code style Joe Perches <joe@perches.com> - 2015-09-03 08:00 +0200
Re: [PATCH v4 01/16] drm: exynos/dp: fix code style Yakir Yang <ykk@rock-chips.com> - 2015-09-06 03:40 +0200
Re: [PATCH v4 01/16] drm: exynos/dp: fix code style Yakir Yang <ykk@rock-chips.com> - 2015-09-03 07:10 +0200
[PATCH v4 04/16] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:00 +0200
[PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:00 +0200
Re: [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-03 10:10 +0200
Re: [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry Yakir Yang <ykk@rock-chips.com> - 2015-09-06 04:10 +0200
[PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:10 +0200
Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-04 02:40 +0200
Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Yakir Yang <ykk@rock-chips.com> - 2015-09-06 06:10 +0200
Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-07 02:00 +0200
Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Yakir Yang <ykk@rock-chips.com> - 2015-09-07 03:50 +0200
[PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:10 +0200
Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Heiko Stuebner <heiko@sntech.de> - 2015-09-01 16:30 +0200
Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Yakir Yang <ykk@rock-chips.com> - 2015-09-01 16:50 +0200
Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Heiko Stuebner <heiko@sntech.de> - 2015-09-01 23:10 +0200
Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Yakir Yang <ykk@rock-chips.com> - 2015-09-02 04:00 +0200
[PATCH v4 06/16] Documentation: drm/bridge: add document for analogix_dp Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:10 +0200
[PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:10 +0200
Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Heiko Stuebner <heiko@sntech.de> - 2015-09-01 23:10 +0200
Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Yakir Yang <ykk@rock-chips.com> - 2015-09-02 04:10 +0200
Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Thierry Reding <treding@nvidia.com> - 2015-09-02 10:40 +0200
Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Yakir Yang <ykk@rock-chips.com> - 2015-09-02 12:10 +0200
Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Thierry Reding <treding@nvidia.com> - 2015-09-03 10:40 +0200
Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Yakir Yang <ykk@rock-chips.com> - 2015-09-06 04:10 +0200
[PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:10 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Heiko Stuebner <heiko@sntech.de> - 2015-09-01 19:00 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Heiko Stuebner <heiko@sntech.de> - 2015-09-01 23:00 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Yakir Yang <ykk@rock-chips.com> - 2015-09-02 03:50 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Yakir Yang <ykk@rock-chips.com> - 2015-09-02 03:10 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Rob Herring <robherring2@gmail.com> - 2015-09-02 15:30 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Yakir Yang <ykk@rock-chips.com> - 2015-09-03 05:30 +0200
Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Heiko Stuebner <heiko@sntech.de> - 2015-09-03 16:00 +0200
[PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:10 +0200
Re: [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-03 02:10 +0200
[PATCH v4 15/16] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:20 +0200
[PATCH v4 12/16] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:20 +0200
[PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:20 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Rob Herring <robherring2@gmail.com> - 2015-09-02 22:20 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang <ykk@rock-chips.com> - 2015-09-03 06:30 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Thierry Reding <treding@nvidia.com> - 2015-09-03 11:10 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Russell King - ARM Linux <linux@arm.linux.org.uk> - 2015-09-04 12:30 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Thierry Reding <treding@nvidia.com> - 2015-09-07 10:30 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Rob Herring <robherring2@gmail.com> - 2015-09-04 23:50 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang <ykk@rock-chips.com> - 2015-09-06 10:30 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Thierry Reding <treding@nvidia.com> - 2015-09-07 10:40 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Thierry Reding <treding@nvidia.com> - 2015-09-03 10:50 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Rob Herring <robherring2@gmail.com> - 2015-09-04 00:00 +0200
Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Thierry Reding <treding@nvidia.com> - 2015-09-04 12:10 +0200
[PATCH v4 13/16] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:20 +0200
[PATCH v4 16/16] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang <ykk@rock-chips.com> - 2015-09-01 08:30 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Heiko Stuebner <heiko@sntech.de> - 2015-09-01 22:50 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang <ykk@rock-chips.com> - 2015-09-02 03:50 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Rob Herring <robherring2@gmail.com> - 2015-09-04 23:10 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Heiko Stuebner <heiko@sntech.de> - 2015-09-04 23:40 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Thierry Reding <treding@nvidia.com> - 2015-09-07 10:20 +0200
Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver Heiko Stuebner <heiko@sntech.de> - 2015-09-02 00:20 +0200
Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver Yakir Yang <ykk@rock-chips.com> - 2015-09-02 04:20 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Emil Velikov <emil.l.velikov@gmail.com> - 2015-09-02 17:00 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang <ykk@rock-chips.com> - 2015-09-03 06:00 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-03 03:00 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang <ykk@rock-chips.com> - 2015-09-03 07:40 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-04 02:50 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang <ykk@rock-chips.com> - 2015-09-06 10:00 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-09-07 02:30 +0200
Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang <ykk@rock-chips.com> - 2015-09-07 04:30 +0200
Page 2 of 4 — ← Prev page 1 [2] 3 4 Next page →
| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Date | 2015-09-01 23:10 +0200 |
| Subject | Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver |
| Message-ID | <q40Yy-1iq-11@gated-at.bofh.it> |
| In reply to | #1216612 |
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
>
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
> dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
> core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
>
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
> and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
> leave those clock to rockchip dp phy driver.
>
> .../bindings/video/analogix_dp-rockchip.txt | 74 ++++
> drivers/gpu/drm/rockchip/Kconfig | 9 +
> drivers/gpu/drm/rockchip/Makefile | 1 +
> drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +
> +- clock-names: from common clock binding:
> + Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> + dp-controller: dp@ff970000 {
> + compatible = "rockchip,rk3288-dp";
> + reg = <0xff970000 0x4000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> + clock-names = "dp", "pclk";
> + phys = <&dp_phy>;
> + phy-names = "dp";
> +
> + rockchip,grf = <&grf>;
> + resets = <&cru 111>;
> + reset-names = "dp";
> +
> + status = "disabled";
> +
> + ports {
#address-cells = <1>;
#size-cells = <0>;
> + edp_in: port {
edp_in: port@0
reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_in_vopb: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_edp>;
> + };
> + edp_in_vopl: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_edp>;
> + };
> + };
> +
> + edp_out: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_out_panel: endpoint {
> + reg = <0>;
> + remote-endpoint = <&panel_in_edp>
> + };
> + };
> + };
> + };
> +
> diff --git a/drivers/gpu/drm/rockchip/Kconfig
> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
> for the Synopsys DesignWare HDMI driver. If you want to
> enable HDMI on RK3288 based SoC, you should selet this
> option.
> +
> +config ROCKCHIP_ANALOGIX_DP
> + tristate "Rockchip specific extensions for Analogix DP driver"
> + depends on DRM_ROCKCHIP
> + select DRM_ANALOGIX_DP
> + help
> + This selects support for Rockchip SoC specific extensions
> + for the Analogix Core DP driver. If you want to enable DP
> + on RK3288 based SoC, you should selet this option.
> diff --git a/drivers/gpu/drm/rockchip/Makefile
> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
>
> obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>
> obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
> index 0000000..cebff9e
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -0,0 +1,389 @@
> +/*
> + * Rockchip SoC DP (Display Port) interface driver.
> + *
> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + * Yakir Yang <ykk@rock-chips.com>
> + * Jeff Chen <jeff.chen@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_graph.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/clk.h>
> +
> +#include <video/of_videomode.h>
> +#include <video/videomode.h>
> +
> +#include <drm/bridge/analogix_dp.h>
> +
> +#include "rockchip_drm_drv.h"
> +#include "rockchip_drm_vop.h"
> +
> +#define encoder_to_dp(c) \
> + container_of(c, struct rockchip_dp_device, encoder)
> +
> +#define plat_data_to_dp(pd) \
> + container_of(pd, struct rockchip_dp_device, plat_data)
> +
> +/* dp grf register offset */
> +#define GRF_GPIO7B_IOMUX 0x0070
> +#define GPIO7B3_SEL_MASK (0x03 << 6)
> +#define GPIO7B3_SEL_EDP_HOTPLUG BIT(7)
please remove, see comment near pre_init
> +
> +#define GRF_SOC_CON6 0x025c
> +#define GRF_EDP_LCD_SEL_MASK BIT(5)
> +#define GRF_EDP_SEL_VOP_LIT BIT(5)
> +#define GRF_EDP_SEL_VOP_BIG 0
> +
> +struct rockchip_dp_device {
> + struct drm_device *drm_dev;
> + struct device *dev;
> + struct drm_encoder encoder;
> + struct drm_display_mode mode;
> +
> + struct clk *pclk;
> + struct regmap *grf;
> + struct reset_control *rst;
> +
> + struct analogix_dp_plat_data plat_data;
> +};
> +
> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
> +{
> + u32 val;
> + int ret;
> +
> + val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
> + ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
this is just a regular pinctrl setting. Please don't write onto other
components registers. Use a regular pinctrl setting in the devicetree instead.
> + if (ret != 0) {
> + dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
> + return ret;
> + }
> +
> + reset_control_assert(dp->rst);
> + usleep_range(10, 20);
> + reset_control_deassert(dp->rst);
> +
> + return 0;
> +}
Heiko
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-02 04:00 +0200 |
| Subject | Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver |
| Message-ID | <q45vc-7yc-11@gated-at.bofh.it> |
| In reply to | #1217083 |
Hi Heiko,
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform driver.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Remove some deprecated DT properties in rockchip dp document.
>>
>> Changes in v3:
>> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>> dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>> core driver which name to "dp", and leave "pclk_edp" to rockchip dp
>> platform driver which name to "pclk".
>> - Take Heiko suggest, add devicetree binding document.
>> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
>> remote point to get panel node.
>> - Add the new function point analogix_dp_platdata.get_modes init.
>>
>> Changes in v2:
>> - Take Heiko suggest, get panel node with remote-endpoint method,
>> and create devicetree binding for driver.
>> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>> leave those clock to rockchip dp phy driver.
>>
>> .../bindings/video/analogix_dp-rockchip.txt | 74 ++++
>> drivers/gpu/drm/rockchip/Kconfig | 9 +
>> drivers/gpu/drm/rockchip/Makefile | 1 +
>> drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 389
>> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
>> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>
>> diff --git
>> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
>> mode 100644
>> index 0000000..502483e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -0,0 +1,74 @@
>> +Rockchip RK3288 specific extensions to the Analogix Display Port
>> +================================
>> +
>> +Required properties:
>> +- compatible: "rockchip,rk3288-edp";
>> +
>> +- reg: physical base address of the controller and length
>> +
>> +- clocks: from common clock binding: handle to dp clock.
>> + of memory mapped region.
>> +
>> +- clock-names: from common clock binding:
>> + Required elements: "dp" "pclk"
>> +
>> +- resets: Must contain an entry for each entry in reset-names.
>> + See ../reset/reset.txt for details.
>> +
>> +- reset-names: Must include the name "dp"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: contain a port node with endpoint definitions as defined in
>> + Documentation/devicetree/bindings/media/video-interfaces.txt.
>> +
>> +
>> +For the below properties, please refer to Analogix DP binding document:
>> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +- phys (required)
>> +- phy-names (required)
>> +- hpd-gpios (optional)
>> +---------------------------------------------------------------------------
>> ---- +
>> +Example:
>> + dp-controller: dp@ff970000 {
>> + compatible = "rockchip,rk3288-dp";
>> + reg = <0xff970000 0x4000>;
>> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
>> + clock-names = "dp", "pclk";
>> + phys = <&dp_phy>;
>> + phy-names = "dp";
>> +
>> + rockchip,grf = <&grf>;
>> + resets = <&cru 111>;
>> + reset-names = "dp";
>> +
>> + status = "disabled";
>> +
>> + ports {
> #address-cells = <1>;
> #size-cells = <0>;
Done,
>> + edp_in: port {
> edp_in: port@0
> reg = <0>;
Done,
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + edp_in_vopb: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&vopb_out_edp>;
>> + };
>> + edp_in_vopl: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&vopl_out_edp>;
>> + };
>> + };
>> +
>> + edp_out: port@1 {
>> + reg = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + edp_out_panel: endpoint {
>> + reg = <0>;
>> + remote-endpoint = <&panel_in_edp>
>> + };
>> + };
>> + };
>> + };
>> +
>> diff --git a/drivers/gpu/drm/rockchip/Kconfig
>> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
>> --- a/drivers/gpu/drm/rockchip/Kconfig
>> +++ b/drivers/gpu/drm/rockchip/Kconfig
>> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
>> for the Synopsys DesignWare HDMI driver. If you want to
>> enable HDMI on RK3288 based SoC, you should selet this
>> option.
>> +
>> +config ROCKCHIP_ANALOGIX_DP
>> + tristate "Rockchip specific extensions for Analogix DP driver"
>> + depends on DRM_ROCKCHIP
>> + select DRM_ANALOGIX_DP
>> + help
>> + This selects support for Rockchip SoC specific extensions
>> + for the Analogix Core DP driver. If you want to enable DP
>> + on RK3288 based SoC, you should selet this option.
>> diff --git a/drivers/gpu/drm/rockchip/Makefile
>> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
>> --- a/drivers/gpu/drm/rockchip/Makefile
>> +++ b/drivers/gpu/drm/rockchip/Makefile
>> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
>> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
>>
>> obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
>> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>>
>> obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
>> index 0000000..cebff9e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -0,0 +1,389 @@
>> +/*
>> + * Rockchip SoC DP (Display Port) interface driver.
>> + *
>> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
>> + * Author: Andy Yan <andy.yan@rock-chips.com>
>> + * Yakir Yang <ykk@rock-chips.com>
>> + * Jeff Chen <jeff.chen@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +#include <drm/drmP.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_panel.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_dp_helper.h>
>> +
>> +#include <linux/component.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/of_graph.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +#include <linux/clk.h>
>> +
>> +#include <video/of_videomode.h>
>> +#include <video/videomode.h>
>> +
>> +#include <drm/bridge/analogix_dp.h>
>> +
>> +#include "rockchip_drm_drv.h"
>> +#include "rockchip_drm_vop.h"
>> +
>> +#define encoder_to_dp(c) \
>> + container_of(c, struct rockchip_dp_device, encoder)
>> +
>> +#define plat_data_to_dp(pd) \
>> + container_of(pd, struct rockchip_dp_device, plat_data)
>> +
>> +/* dp grf register offset */
>> +#define GRF_GPIO7B_IOMUX 0x0070
>> +#define GPIO7B3_SEL_MASK (0x03 << 6)
>> +#define GPIO7B3_SEL_EDP_HOTPLUG BIT(7)
> please remove, see comment near pre_init
Okay,
>
>> +
>> +#define GRF_SOC_CON6 0x025c
>> +#define GRF_EDP_LCD_SEL_MASK BIT(5)
>> +#define GRF_EDP_SEL_VOP_LIT BIT(5)
>> +#define GRF_EDP_SEL_VOP_BIG 0
>> +
>> +struct rockchip_dp_device {
>> + struct drm_device *drm_dev;
>> + struct device *dev;
>> + struct drm_encoder encoder;
>> + struct drm_display_mode mode;
>> +
>> + struct clk *pclk;
>> + struct regmap *grf;
>> + struct reset_control *rst;
>> +
>> + struct analogix_dp_plat_data plat_data;
>> +};
>> +
>> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
>> +{
>> + u32 val;
>> + int ret;
>> +
>> + val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
>> + ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
> this is just a regular pinctrl setting. Please don't write onto other
> components registers. Use a regular pinctrl setting in the devicetree instead.
Okay,
Thanks,
- Yakir
>
>> + if (ret != 0) {
>> + dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + reset_control_assert(dp->rst);
>> + usleep_range(10, 20);
>> + reset_control_deassert(dp->rst);
>> +
>> + return 0;
>> +}
>
> Heiko
>
>
>
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-01 08:10 +0200 |
| Subject | [PATCH v4 06/16] Documentation: drm/bridge: add document for analogix_dp |
| Message-ID | <q3MVA-6v2-9@gated-at.bofh.it> |
| In reply to | #1216602 |
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, split all DTS changes, and provide backward compatibility.
Mark old properties as deprecated but still support them.
- Take Rob suggest, update "analogix,hpd-gpio" to "hpd-gpios" prop name.
- Take Thierry suggest, deprecated some properties which could parsed from Edid/Mode/DPCD.
"analogix,color-space" & "analogix,color-depth" &
"analogix,link-rate" & "analogix,lane-count" &
"analogix,ycbcr-coeff" & "analogix,dynamic-range" &
"vsync-active-high" & "hsync-active-high" & "interlaces"
Changes in v3:
- Take Heiko suggest, add devicetree binding documents.
- Take Thierry Reding suggest, remove sync pol & colorimetry properies
from the new analogix dp driver devicetree binding.
- Update the exist exynos dtsi file with the latest DP DT properies.
Changes in v2: None
.../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
.../devicetree/bindings/video/exynos_dp.txt | 63 ++++++++--------------
2 files changed, 71 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+ -compatible:
+ platform specific such as:
+ * "samsung,exynos5-dp"
+ * "rockchip,rk3288-dp"
+ -reg:
+ physical base address of the controller and length
+ of memory mapped region.
+ -interrupts:
+ interrupt combiner values.
+ -clocks:
+ from common clock binding: handle to dp clock.
+ -clock-names:
+ from common clock binding: Shall be "dp".
+ -interrupt-parent:
+ phandle to Interrupt combiner node.
+ -phys:
+ from general PHY binding: the phandle for the PHY device.
+ -phy-names:
+ from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+ -hpd-gpios:
+ Hotplug detect GPIO.
+ Indicates which GPIO should be used for hotplug detection
+ -port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+ * Documentation/devicetree/bindings/video/exynos_dp.txt
+ * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+ dp-controller {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x10000>;
+ interrupts = <10 3>;
+ interrupt-parent = <&combiner>;
+ clocks = <&clock 342>;
+ clock-names = "dp";
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+ };
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
from general PHY binding: the phandle for the PHY device.
-phy-names:
from general PHY binding: Should be "dp".
- -samsung,color-space:
- input video data format.
- COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
- -samsung,dynamic-range:
- dynamic range for input video data.
- VESA = 0, CEA = 1
- -samsung,ycbcr-coeff:
- YCbCr co-efficients for input video.
- COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
- -samsung,color-depth:
- number of bits per colour component.
- COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
- -samsung,link-rate:
- link rate supported by the panel.
- LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
- -samsung,lane-count:
- number of lanes supported by the panel.
- LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
- display-timings: timings for the connected panel as described by
Documentation/devicetree/bindings/video/display-timing.txt
-Optional properties for dp-controller:
- -interlaced:
- interlace scan mode.
- Progressive if defined, Interlaced if not defined
- -vsync-active-high:
- VSYNC polarity configuration.
- High if defined, Low if not defined
- -hsync-active-high:
- HSYNC polarity configuration.
- High if defined, Low if not defined
- -samsung,hpd-gpio:
- Hotplug detect GPIO.
- Indicates which GPIO should be used for hotplug
- detection
- -video interfaces: Device node can contain video interface port
- nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+ -phys (required)
+ -phy-names (required)
+ -hpd-gpios (optional)
+ -video interfaces (optional)
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced: deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high: deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high: deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff: deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space: deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio: deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
Example:
@@ -88,13 +74,6 @@ SOC specific portion:
Board Specific portion:
dp-controller {
- samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
- samsung,color-depth = <1>;
- samsung,link-rate = <0x0a>;
- samsung,lane-count = <4>;
-
display-timings {
native-mode = <&lcd_timing>;
lcd_timing: 1366x768 {
--
2.1.2
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-01 08:10 +0200 |
| Subject | [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q3MVA-6v2-13@gated-at.bofh.it> |
| In reply to | #1216602 |
From: Mark Yao <yzq@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46 +++++++++++++++++++------
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 33 ++++++++++++++++--
4 files changed, 68 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index cebff9e..efea045 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -11,11 +11,6 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_of.h>
-#include <drm/drm_dp_helper.h>
#include <linux/component.h>
#include <linux/mfd/syscon.h>
@@ -27,6 +22,13 @@
#include <video/of_videomode.h>
#include <video/videomode.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
#include <drm/bridge/analogix_dp.h>
#include "rockchip_drm_drv.h"
@@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
/* do nothing */
}
+static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device *dp)
+{
+ struct drm_connector *connector;
+ struct drm_device *drm_dev = dp->drm_dev;
+
+ drm_for_each_connector(connector, drm_dev) {
+ if (connector->encoder != &dp->encoder)
+ return connector;
+ }
+
+ return NULL;
+}
+
static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
{
struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+ struct drm_connector *connector;
+ int ret = 0;
u32 val;
- int ret;
- ret = rockchip_drm_crtc_mode_config(encoder->crtc,
- DRM_MODE_CONNECTOR_eDP,
- ROCKCHIP_OUT_MODE_AAAA);
- if (ret < 0) {
+ connector = rockchip_dp_get_connector(dp);
+ if (!connector) {
+ DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
+ return;
+ }
+
+ if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
+ ret = rockchip_drm_crtc_mode_config(
+ encoder->crtc, DRM_MODE_CONNECTOR_eDP,
+ connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
+ if (!ret) {
dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
return;
}
+ connector->display_info.bpc = ret;
+ connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
+
ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
if (ret < 0)
return;
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
{
rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
- ROCKCHIP_OUT_MODE_AAAA);
+ 10, DRM_COLOR_FORMAT_RGB444);
}
static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
int rockchip_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
- int out_mode);
+ int bpc, int color);
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
struct device *dev);
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 34b78e7..5d7f9b6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs = {
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
int connector_type,
- int out_mode)
+ int bpc, int color)
{
struct vop *vop = to_vop(crtc);
-
vop->connector_type = connector_type;
vop->connector_out_mode = out_mode;
- return 0;
+ /*
+ * RK3288 vop only support RGB Color output.
+ */
+ if (color != DRM_COLOR_FORMAT_RGB444) {
+ DRM_ERROR("Only support output RGB444, not support%d\n",
+ color);
+ return -EINVAL;
+ }
+
+ /*
+ * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+ * bpc, 5 or 6?
+ *
+ */
+ if (bpc >= 10) {
+ bpc = 10;
+ vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+ } else if (bpc >= 8) {
+ bpc = 8;
+ vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+ } else if (bpc >= 6) {
+ bpc = 6;
+ vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+ } else {
+ DRM_ERROR("unsupport bpc %d\n", bpc);
+ return -EINVAL;
+ }
+
+ return bpc;
}
EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
--
2.1.2
--
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[toc] | [prev] | [next] | [standalone]
| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Date | 2015-09-01 23:10 +0200 |
| Subject | Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q40Yy-1iq-1@gated-at.bofh.it> |
| In reply to | #1216614 |
Hi Yakir,
Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> From: Mark Yao <yzq@rock-chips.com>
>
> Add bpc and color mode setting in rockchip_drm_vop driver, so
> connector could try to use the edid drm_display_info to config
> vop output mode.
>
> Signed-off-by: Mark Yao <yzq@rock-chips.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c |
> 2 +-
> drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 33 ++++++++++++++++--
> 4 files changed, 68 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
> 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -11,11 +11,6 @@
> * Free Software Foundation; either version 2 of the License, or (at your
> * option) any later version.
> */
> -#include <drm/drmP.h>
> -#include <drm/drm_crtc_helper.h>
> -#include <drm/drm_panel.h>
> -#include <drm/drm_of.h>
> -#include <drm/drm_dp_helper.h>
>
> #include <linux/component.h>
> #include <linux/mfd/syscon.h>
> @@ -27,6 +22,13 @@
> #include <video/of_videomode.h>
> #include <video/videomode.h>
>
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
> #include <drm/bridge/analogix_dp.h>
>
> #include "rockchip_drm_drv.h"
> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
> drm_encoder *encoder, /* do nothing */
> }
>
> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device
missing a "struct" -> static struct drm_connector
> *dp) +{
> + struct drm_connector *connector;
> + struct drm_device *drm_dev = dp->drm_dev;
> +
> + drm_for_each_connector(connector, drm_dev) {
> + if (connector->encoder != &dp->encoder)
> + return connector;
> + }
> +
> + return NULL;
> +}
> +
> static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
> {
> struct rockchip_dp_device *dp = encoder_to_dp(encoder);
> + struct drm_connector *connector;
> + int ret = 0;
> u32 val;
> - int ret;
>
> - ret = rockchip_drm_crtc_mode_config(encoder->crtc,
> - DRM_MODE_CONNECTOR_eDP,
> - ROCKCHIP_OUT_MODE_AAAA);
> - if (ret < 0) {
> + connector = rockchip_dp_get_connector(dp);
> + if (!connector) {
> + DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
> + return;
> + }
> +
> + if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
> + ret = rockchip_drm_crtc_mode_config(
> + encoder->crtc, DRM_MODE_CONNECTOR_eDP,
> + connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
> + if (!ret) {
> dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
> return;
> }
>
> + connector->display_info.bpc = ret;
> + connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
> +
> ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
> if (ret < 0)
> return;
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
> drm_encoder *encoder) {
> rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
> - ROCKCHIP_OUT_MODE_AAAA);
> + 10, DRM_COLOR_FORMAT_RGB444);
> }
>
> static struct drm_encoder_helper_funcs
> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
> *node,
> struct drm_encoder *encoder);
> int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
> connector_type, - int out_mode);
> + int bpc, int color);
> int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
> struct device *dev);
> void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> {
>
> int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
> int connector_type,
> - int out_mode)
> + int bpc, int color)
> {
> struct vop *vop = to_vop(crtc);
> -
> vop->connector_type = connector_type;
> vop->connector_out_mode = out_mode;
this line should probably go away, as the source var "out_mode" does not exist
in the function params any more, making the compilation break, and is set
below anyway.
Heiko
>
> - return 0;
> + /*
> + * RK3288 vop only support RGB Color output.
> + */
> + if (color != DRM_COLOR_FORMAT_RGB444) {
> + DRM_ERROR("Only support output RGB444, not support%d\n",
> + color);
> + return -EINVAL;
> + }
> +
> + /*
> + * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
> + * bpc, 5 or 6?
> + *
> + */
> + if (bpc >= 10) {
> + bpc = 10;
> + vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
> + } else if (bpc >= 8) {
> + bpc = 8;
> + vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> + } else if (bpc >= 6) {
> + bpc = 6;
> + vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> + } else {
> + DRM_ERROR("unsupport bpc %d\n", bpc);
> + return -EINVAL;
> + }
> +
> + return bpc;
> }
> EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
--
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-02 04:10 +0200 |
| Subject | Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q45ER-7Yy-1@gated-at.bofh.it> |
| In reply to | #1217082 |
Hi Heiko,
在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
>> From: Mark Yao <yzq@rock-chips.com>
>>
>> Add bpc and color mode setting in rockchip_drm_vop driver, so
>> connector could try to use the edid drm_display_info to config
>> vop output mode.
>>
>> Signed-off-by: Mark Yao <yzq@rock-chips.com>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
>> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c |
>> 2 +-
>> drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 33 ++++++++++++++++--
>> 4 files changed, 68 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
>> 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -11,11 +11,6 @@
>> * Free Software Foundation; either version 2 of the License, or (at your
>> * option) any later version.
>> */
>> -#include <drm/drmP.h>
>> -#include <drm/drm_crtc_helper.h>
>> -#include <drm/drm_panel.h>
>> -#include <drm/drm_of.h>
>> -#include <drm/drm_dp_helper.h>
>>
>> #include <linux/component.h>
>> #include <linux/mfd/syscon.h>
>> @@ -27,6 +22,13 @@
>> #include <video/of_videomode.h>
>> #include <video/videomode.h>
>>
>> +#include <drm/drmP.h>
>> +#include <drm/drm_crtc.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_panel.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_dp_helper.h>
>> +
>> #include <drm/bridge/analogix_dp.h>
>>
>> #include "rockchip_drm_drv.h"
>> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
>> drm_encoder *encoder, /* do nothing */
>> }
>>
>> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device
> missing a "struct" -> static struct drm_connector
What the hell mistake I make in v5 :-(
Thanks a lot, I would fix this as soon as possible
>
>> *dp) +{
>> + struct drm_connector *connector;
>> + struct drm_device *drm_dev = dp->drm_dev;
>> +
>> + drm_for_each_connector(connector, drm_dev) {
>> + if (connector->encoder != &dp->encoder)
>> + return connector;
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
>> {
>> struct rockchip_dp_device *dp = encoder_to_dp(encoder);
>> + struct drm_connector *connector;
>> + int ret = 0;
>> u32 val;
>> - int ret;
>>
>> - ret = rockchip_drm_crtc_mode_config(encoder->crtc,
>> - DRM_MODE_CONNECTOR_eDP,
>> - ROCKCHIP_OUT_MODE_AAAA);
>> - if (ret < 0) {
>> + connector = rockchip_dp_get_connector(dp);
>> + if (!connector) {
>> + DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
>> + return;
>> + }
>> +
>> + if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
>> + ret = rockchip_drm_crtc_mode_config(
>> + encoder->crtc, DRM_MODE_CONNECTOR_eDP,
>> + connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
>> + if (!ret) {
>> dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
>> return;
>> }
>>
>> + connector->display_info.bpc = ret;
>> + connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
>> +
>> ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
>> if (ret < 0)
>> return;
>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
>> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
>> drm_encoder *encoder) {
>> rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
>> - ROCKCHIP_OUT_MODE_AAAA);
>> + 10, DRM_COLOR_FORMAT_RGB444);
>> }
>>
>> static struct drm_encoder_helper_funcs
>> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
>> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
>> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
>> *node,
>> struct drm_encoder *encoder);
>> int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
>> connector_type, - int out_mode);
>> + int bpc, int color);
>> int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
>> struct device *dev);
>> void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
>> {
>>
>> int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>> int connector_type,
>> - int out_mode)
>> + int bpc, int color)
>> {
>> struct vop *vop = to_vop(crtc);
>> -
>> vop->connector_type = connector_type;
>> vop->connector_out_mode = out_mode;
> this line should probably go away, as the source var "out_mode" does not exist
> in the function params any more, making the compilation break, and is set
> below anyway.
Sorry for the failed, there are must be a problem when I backport those code
to chrome-3.14 to verify.
Thanks a lot, I would update next version soon.
- Yakir
>
> Heiko
>
>> - return 0;
>> + /*
>> + * RK3288 vop only support RGB Color output.
>> + */
>> + if (color != DRM_COLOR_FORMAT_RGB444) {
>> + DRM_ERROR("Only support output RGB444, not support%d\n",
>> + color);
>> + return -EINVAL;
>> + }
>> +
>> + /*
>> + * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
>> + * bpc, 5 or 6?
>> + *
>> + */
>> + if (bpc >= 10) {
>> + bpc = 10;
>> + vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
>> + } else if (bpc >= 8) {
>> + bpc = 8;
>> + vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
>> + } else if (bpc >= 6) {
>> + bpc = 6;
>> + vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
>> + } else {
>> + DRM_ERROR("unsupport bpc %d\n", bpc);
>> + return -EINVAL;
>> + }
>> +
>> + return bpc;
>> }
>> EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
>
>
>
--
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| From | Thierry Reding <treding@nvidia.com> |
|---|---|
| Date | 2015-09-02 10:40 +0200 |
| Subject | Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q4bKi-8dy-19@gated-at.bofh.it> |
| In reply to | #1217275 |
[Multipart message — attachments visible in raw view] — view raw
On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
> 在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> >Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
[...]
> >>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> >>--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> >>{
> >>
> >> int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
> >> int connector_type,
> >>- int out_mode)
> >>+ int bpc, int color)
> >> {
> >> struct vop *vop = to_vop(crtc);
> >>-
> >> vop->connector_type = connector_type;
> >> vop->connector_out_mode = out_mode;
> >this line should probably go away, as the source var "out_mode" does not exist
> >in the function params any more, making the compilation break, and is set
> >below anyway.
>
> Sorry for the failed, there are must be a problem when I backport those code
> to chrome-3.14 to verify.
>
> Thanks a lot, I would update next version soon.
*sigh*
I get the feeling that you're going about upstreaming the wrong way. If
you post patches to upstream mailing lists and you expect people to
apply those patches, then your target is the upstream kernel. So you
should be basing all of your work on top of a recent release candidate
directly from Linus or some recent version of linux-next.
Your current approach is already making people waste time trying to
build the patches and fail because you've been testing on something
other than mainline or linux-next.
At the very least your code must compile when applied against a recent
upstream tree. I would also expect you to make sure the code works at
runtime, though, contrary to build testing, not everybody will be able
to verify that you've actually done so. It is ultimately your platform
maintainer's (i.e. Heiko's) responsibility to ensure that because they
will get to deal with user complaints if people can't run an upstream
kernel on the devices.
I realize that the upstream kernel isn't what's going to end up in
products later on, but that doesn't change the fact that you're
submitting code for inclusion in the mainline tree. If you need to
backport code to some ChromeOS tree, then that should be done after
you've verified that things build and run upstream. Doing so makes life
a lot easier for your upstream maintainers, and that in turn makes it
more likely to get your code merged.
Thierry
[toc] | [prev] | [next] | [standalone]
| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-02 12:10 +0200 |
| Subject | Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q4d9n-1Ut-17@gated-at.bofh.it> |
| In reply to | #1217418 |
Thierry,
在 2015/9/2 16:34, Thierry Reding 写道:
> On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
>> 在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
>>> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> [...]
>>>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
>>>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
>>>> {
>>>>
>>>> int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>>>> int connector_type,
>>>> - int out_mode)
>>>> + int bpc, int color)
>>>> {
>>>> struct vop *vop = to_vop(crtc);
>>>> -
>>>> vop->connector_type = connector_type;
>>>> vop->connector_out_mode = out_mode;
>>> this line should probably go away, as the source var "out_mode" does not exist
>>> in the function params any more, making the compilation break, and is set
>>> below anyway.
>> Sorry for the failed, there are must be a problem when I backport those code
>> to chrome-3.14 to verify.
>>
>> Thanks a lot, I would update next version soon.
> *sigh*
>
> I get the feeling that you're going about upstreaming the wrong way. If
> you post patches to upstream mailing lists and you expect people to
> apply those patches, then your target is the upstream kernel. So you
> should be basing all of your work on top of a recent release candidate
> directly from Linus or some recent version of linux-next.
Yeah, do feel I am in the wrong way now. I used to write my patch on
linux-next branch, then backport some head file to productor kernel,
so I can check compiled failed. After that, I backport the dp driver code
to normal productor kernel, start to debug the function.
So I used to ensure no compiled failed on upstrean kernel, actually it's
also hard to ensure, cause I just backport head file. Not even debug the
function on upstream kernel.
> Your current approach is already making people waste time trying to
> build the patches and fail because you've been testing on something
> other than mainline or linux-next.
>
> At the very least your code must compile when applied against a recent
> upstream tree. I would also expect you to make sure the code works at
> runtime, though, contrary to build testing, not everybody will be able
> to verify that you've actually done so. It is ultimately your platform
> maintainer's (i.e. Heiko's) responsibility to ensure that because they
> will get to deal with user complaints if people can't run an upstream
> kernel on the devices.
Oh, first time to know this rule. So I should work on Heiko's github
kernel branch at the first time to start send upstream.
> I realize that the upstream kernel isn't what's going to end up in
> products later on, but that doesn't change the fact that you're
> submitting code for inclusion in the mainline tree. If you need to
> backport code to some ChromeOS tree, then that should be done after
> you've verified that things build and run upstream. Doing so makes life
> a lot easier for your upstream maintainers, and that in turn makes it
> more likely to get your code merged.
Feel free now, I would correct those in bellow version. Thanks
for your remind (or maybe complain :-D ).
- Yakir
> Thierry
--
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[toc] | [prev] | [next] | [standalone]
| From | Thierry Reding <treding@nvidia.com> |
|---|---|
| Date | 2015-09-03 10:40 +0200 |
| Subject | Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q4ydQ-6Hz-23@gated-at.bofh.it> |
| In reply to | #1217472 |
[Multipart message — attachments visible in raw view] — view raw
On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote: > 在 2015/9/2 16:34, Thierry Reding 写道: [...] > >At the very least your code must compile when applied against a recent > >upstream tree. I would also expect you to make sure the code works at > >runtime, though, contrary to build testing, not everybody will be able > >to verify that you've actually done so. It is ultimately your platform > >maintainer's (i.e. Heiko's) responsibility to ensure that because they > >will get to deal with user complaints if people can't run an upstream > >kernel on the devices. > > Oh, first time to know this rule. So I should work on Heiko's github > kernel branch at the first time to start send upstream. It's usually not necessary to rebase on a specific platform tree. Most platform trees should feed into linux-next anyway, so linux-next would be the appropriate base in almost all cases. Note, though, that that's only true if you expect somebody else to merge your code. The reason is that whoever will end up applying your patches will likely apply to a tree that feeds into linux-next, and that way you both end up having roughly the same base. On the other hand if you are a maintainer yourself you should be keeping a branch based on the latest -rc1. That's especially important if your tree feeds into linux-next, because basing on linux-next will break very horribly that way. So for this particular case I would expect either Mark or Inki to apply these patches when they're ready. Their trees should be based on the latest -rc1. At least the Exynos DRM tree feeds into linux-next, so you should be fine if you use linux-next as a base. Mark, have you ever considered having your tree added to linux-next? I'm beginning to think that we need to make that a requirement for all DRM drivers so that we can resolve integration issues early on rather than Dave having to deal with them when he pulls code in. Thierry
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-06 04:10 +0200 |
| Subject | Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting |
| Message-ID | <q5xz3-1KD-3@gated-at.bofh.it> |
| In reply to | #1218102 |
Hi Thierry, 在 09/03/2015 04:38 PM, Thierry Reding 写道: > On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote: >> 在 2015/9/2 16:34, Thierry Reding 写道: > [...] >>> At the very least your code must compile when applied against a recent >>> upstream tree. I would also expect you to make sure the code works at >>> runtime, though, contrary to build testing, not everybody will be able >>> to verify that you've actually done so. It is ultimately your platform >>> maintainer's (i.e. Heiko's) responsibility to ensure that because they >>> will get to deal with user complaints if people can't run an upstream >>> kernel on the devices. >> Oh, first time to know this rule. So I should work on Heiko's github >> kernel branch at the first time to start send upstream. > It's usually not necessary to rebase on a specific platform tree. Most > platform trees should feed into linux-next anyway, so linux-next would > be the appropriate base in almost all cases. > > Note, though, that that's only true if you expect somebody else to merge > your code. The reason is that whoever will end up applying your patches > will likely apply to a tree that feeds into linux-next, and that way you > both end up having roughly the same base. > > On the other hand if you are a maintainer yourself you should be keeping > a branch based on the latest -rc1. That's especially important if your > tree feeds into linux-next, because basing on linux-next will break very > horribly that way. > > So for this particular case I would expect either Mark or Inki to apply > these patches when they're ready. Their trees should be based on the > latest -rc1. At least the Exynos DRM tree feeds into linux-next, so you > should be fine if you use linux-next as a base. Glad to know this, thanks, - Yakir > > Mark, have you ever considered having your tree added to linux-next? > > I'm beginning to think that we need to make that a requirement for all > DRM drivers so that we can resolve integration issues early on rather > than Dave having to deal with them when he pulls code in. > > Thierry -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-01 08:10 +0200 |
| Subject | [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q3MVA-6v2-15@gated-at.bofh.it> |
| In reply to | #1216602 |
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Kishon suggest, add commit message, and remove the redundant
rockchip_dp_phy_init() function, move those code to probe() method.
And remove driver .owner number.
Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
collect the phy clocks and power control.
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt | 26 ++++
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 166 +++++++++++++++++++++
4 files changed, 200 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
create mode 100644 drivers/phy/phy-rockchip-dp.c
diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..5de1088
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,26 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+ - "rockchip.rk3288-dp-phy"
+
+- reg : a list of registers used by phy driver
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+- clock-names: from common clock binding:
+ Required elements: "sclk_dp" "sclk_dp_24m"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: phy@ff770274 {
+ compatilble = "rockchip,rk3288-dp-phy";
+ reg = <0xff770274 4>;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
+}
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_DP
+ tristate "Rockchip Display Port PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip Display Port PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..e9a726e
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,166 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12 0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define DP_PHY_SIDDQ_WRITE_EN BIT(21)
+#define DP_PHY_SIDDQ_ON 0
+#define DP_PHY_SIDDQ_OFF BIT(5)
+
+struct rockchip_dp_phy {
+ struct device *dev;
+ struct regmap *grf;
+ void __iomem *regs;
+ struct clk *phy_24m;
+};
+
+static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
+{
+ int ret = 0;
+
+ ret = clk_set_rate(dp->phy_24m, 24000000);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
+{
+ clk_disable_unprepare(dp->phy_24m);
+
+ return 0;
+}
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+
+ if (enable) {
+ rockchip_dp_phy_clk_enable(dp);
+ writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
+ } else {
+ rockchip_dp_phy_clk_disable(dp);
+ writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
+ }
+
+ return 0;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, false);
+}
+
+static struct phy_ops rockchip_dp_phy_ops = {
+ .power_on = rockchip_dp_phy_power_on,
+ .power_off = rockchip_dp_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct phy_provider *phy_provider;
+ struct rockchip_dp_phy *dp;
+ struct resource *res;
+ struct phy *phy;
+ int ret;
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (IS_ERR(dp))
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dp->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(dp->regs))
+ return PTR_ERR(dp->regs);
+
+ dp->phy_24m = devm_clk_get(dev, "24m");
+ if (IS_ERR(dp->phy_24m)) {
+ dev_err(dev, "cannot get clock 24m\n");
+ return PTR_ERR(dp->phy_24m);
+ }
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_REF_CLK_SEL_INTER |
+ (GRF_EDP_REF_CLK_SEL_INTER << 16));
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+ return ret;
+ }
+
+ phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, dp);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3288-dp-phy" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+ .probe = rockchip_dp_phy_probe,
+ .driver = {
+ .name = "rockchip-dp-phy",
+ .of_match_table = rockchip_dp_phy_dt_ids,
+ },
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.1.2
--
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| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Date | 2015-09-01 19:00 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q3X4B-3Wm-3@gated-at.bofh.it> |
| In reply to | #1216615 |
Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
> rockchip_dp_phy_init() function, move those code to probe() method.
> And remove driver .owner number.
>
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
> collect the phy clocks and power control.
>
> Changes in v2: None
>
> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 26 ++++
> drivers/phy/Kconfig | 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-dp.c | 166
> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
> 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
> 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> + - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver
nodes do not necessarily need to have a regs property. You can do all
operations via the grf syscon already.
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +- clock-names: from common clock binding:
> + Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy@ff770274 {
edp_phy: edp-phy {
> + compatilble = "rockchip,rk3288-dp-phy";
> + reg = <0xff770274 4>;
no regs property
> + rockchip,grf = <&grf>;
> + clocks = <&cru SCLK_EDP_24M>;
> + clock-names = "24m";
> + #phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> help
> Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> + tristate "Rockchip Display Port PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + help
> + Enable this to support the Rockchip Display Port PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) +=
> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12 0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN BIT(21)
> +#define DP_PHY_SIDDQ_ON 0
> +#define DP_PHY_SIDDQ_OFF BIT(5)
> +
> +struct rockchip_dp_phy {
> + struct device *dev;
> + struct regmap *grf;
> + void __iomem *regs;
> + struct clk *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> + int ret = 0;
> +
> + ret = clk_set_rate(dp->phy_24m, 24000000);
> + if (ret < 0) {
> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(dp->phy_24m);
> + if (ret < 0) {
> + dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> + clk_disable_unprepare(dp->phy_24m);
> +
> + return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> + if (enable) {
> + rockchip_dp_phy_clk_enable(dp);
> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> + } else {
> + rockchip_dp_phy_clk_disable(dp);
> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> + return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> + return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {
static const struct ...
see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")
> + .power_on = rockchip_dp_phy_power_on,
> + .power_off = rockchip_dp_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp_phy *dp;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
I guess this could profit from a
if (!np)
return -ENODEV;
> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> + if (IS_ERR(dp))
> + return -ENOMEM;
> +
> + dp->dev = dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + dp->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(dp->regs))
> + return PTR_ERR(dp->regs);
> +
> + dp->phy_24m = devm_clk_get(dev, "24m");
> + if (IS_ERR(dp->phy_24m)) {
> + dev_err(dev, "cannot get clock 24m\n");
> + return PTR_ERR(dp->phy_24m);
> + }
> +
> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> + if (IS_ERR(dp->grf)) {
> + dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> + return PTR_ERR(dp->grf);
> + }
> +
> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
> + GRF_EDP_REF_CLK_SEL_INTER |
> + (GRF_EDP_REF_CLK_SEL_INTER << 16));
> + if (ret != 0) {
> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> + return ret;
> + }
> +
> + phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
hmm, where did you find 4 params for devm_phy_create? Shouldn't this be
phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
instead - and also include the phy dt-node as 2nd parameter?
Heiko
> + if (IS_ERR(phy)) {
> + dev_err(dev, "failed to create phy\n");
> + return PTR_ERR(phy);
> + }
> + phy_set_drvdata(phy, dp);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> + { .compatible = "rockchip,rk3288-dp-phy" },
> + {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> + .probe = rockchip_dp_phy_probe,
> + .driver = {
> + .name = "rockchip-dp-phy",
> + .of_match_table = rockchip_dp_phy_dt_ids,
> + },
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");
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| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Date | 2015-09-01 23:00 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q40OS-RN-13@gated-at.bofh.it> |
| In reply to | #1216964 |
Hi Yakir,
small nit more below
Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> > +- clocks: from common clock binding: handle to dp clock.
> > + of memory mapped region.
> > +- clock-names: from common clock binding:
> > + Required elements: "sclk_dp" "sclk_dp_24m"
> > +
> > +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > +- #phy-cells : from the generic PHY bindings, must be 0;
> > +
> > +Example:
> > +
> > +edp_phy: phy@ff770274 {
>
> edp_phy: edp-phy {
>
> > + compatilble = "rockchip,rk3288-dp-phy";
typo: compatible
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-02 03:50 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q45lw-7n0-11@gated-at.bofh.it> |
| In reply to | #1217081 |
Hi Heiko,
在 09/02/2015 04:58 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> small nit more below
>
> Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
>> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>>> +- clocks: from common clock binding: handle to dp clock.
>>> + of memory mapped region.
>>> +- clock-names: from common clock binding:
>>> + Required elements: "sclk_dp" "sclk_dp_24m"
>>> +
>>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>>> +- #phy-cells : from the generic PHY bindings, must be 0;
>>> +
>>> +Example:
>>> +
>>> +edp_phy: phy@ff770274 {
>> edp_phy: edp-phy {
>>
>>> + compatilble = "rockchip,rk3288-dp-phy";
> typo: compatible
Aha, thanks.
- Yakir
>
>
>
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-02 03:10 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q44IO-6Dz-29@gated-at.bofh.it> |
| In reply to | #1216964 |
Hi Heiko,
在 09/02/2015 12:51 AM, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>> rockchip_dp_phy_init() function, move those code to probe() method.
>> And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>> collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 26 ++++
>> drivers/phy/Kconfig | 7 +
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-rockchip-dp.c | 166
>> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
>> 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
>> 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> + - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> nodes do not necessarily need to have a regs property. You can do all
> operations via the grf syscon already.
Oh, yes, the dp phy power register is belong to GRF filed, thanks.
>
>> +- clocks: from common clock binding: handle to dp clock.
>> + of memory mapped region.
>> +- clock-names: from common clock binding:
>> + Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy@ff770274 {
> edp_phy: edp-phy {
Done,
>
>
>> + compatilble = "rockchip,rk3288-dp-phy";
>> + reg = <0xff770274 4>;
> no regs property
Done
>> + rockchip,grf = <&grf>;
>> + clocks = <&cru SCLK_EDP_24M>;
>> + clock-names = "24m";
>> + #phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>> help
>> Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> + tristate "Rockchip Display Port PHY Driver"
>> + depends on ARCH_ROCKCHIP && OF
>> + select GENERIC_PHY
>> + help
>> + Enable this to support the Rockchip Display Port PHY.
>> +
>> config PHY_ST_SPEAR1310_MIPHY
>> tristate "ST SPEAR1310-MIPHY driver"
>> select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) +=
>> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
>> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
>> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
>> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
>> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
>> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12 0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN BIT(21)
>> +#define DP_PHY_SIDDQ_ON 0
>> +#define DP_PHY_SIDDQ_OFF BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> + struct device *dev;
>> + struct regmap *grf;
>> + void __iomem *regs;
>> + struct clk *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> + int ret = 0;
>> +
>> + ret = clk_set_rate(dp->phy_24m, 24000000);
>> + if (ret < 0) {
>> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = clk_prepare_enable(dp->phy_24m);
>> + if (ret < 0) {
>> + dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> + clk_disable_unprepare(dp->phy_24m);
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> + if (enable) {
>> + rockchip_dp_phy_clk_enable(dp);
>> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> + } else {
>> + rockchip_dp_phy_clk_disable(dp);
>> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> + return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> + return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
> static const struct ...
>
> see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")
Done, thanks
>
>> + .power_on = rockchip_dp_phy_power_on,
>> + .power_off = rockchip_dp_phy_power_off,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct phy_provider *phy_provider;
>> + struct rockchip_dp_phy *dp;
>> + struct resource *res;
>> + struct phy *phy;
>> + int ret;
>> +
> I guess this could profit from a
>
> if (!np)
> return -ENODEV;
Hmm... so we are avoiding the no of_device case,
Done,
>> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> + if (IS_ERR(dp))
>> + return -ENOMEM;
>> +
>> + dp->dev = dev;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + dp->regs = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(dp->regs))
>> + return PTR_ERR(dp->regs);
>> +
>> + dp->phy_24m = devm_clk_get(dev, "24m");
>> + if (IS_ERR(dp->phy_24m)) {
>> + dev_err(dev, "cannot get clock 24m\n");
>> + return PTR_ERR(dp->phy_24m);
>> + }
>> +
>> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> + if (IS_ERR(dp->grf)) {
>> + dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> + return PTR_ERR(dp->grf);
>> + }
>> +
>> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> + GRF_EDP_REF_CLK_SEL_INTER |
>> + (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> + if (ret != 0) {
>> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + phy = devm(dev, NULL, &rockchip_dp_phy_ops, NULL);
> hmm, where did you find 4 params for devm_phy_create? Shouldn't this be
>
> phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
>
> instead - and also include the phy dt-node as 2nd parameter?
Oh, :-(=
I used to test the driver on chrome-3.14 branch, I always back the drm
head file,
so there would be no drm conflict. But phy driver is missed, the 4
params is come
from kernel-3.14.
Thanks for your redmind,
- Yakir
>
> Heiko
>
>> + if (IS_ERR(phy)) {
>> + dev_err(dev, "failed to create phy\n");
>> + return PTR_ERR(phy);
>> + }
>> + phy_set_drvdata(phy, dp);
>> +
>> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> + { .compatible = "rockchip,rk3288-dp-phy" },
>> + {}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> + .probe = rockchip_dp_phy_probe,
>> + .driver = {
>> + .name = "rockchip-dp-phy",
>> + .of_match_table = rockchip_dp_phy_dt_ids,
>> + },
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>
>
>
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| From | Rob Herring <robherring2@gmail.com> |
|---|---|
| Date | 2015-09-02 15:30 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q4ggW-6j4-9@gated-at.bofh.it> |
| In reply to | #1216615 |
On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
> rockchip_dp_phy_init() function, move those code to probe() method.
> And remove driver .owner number.
>
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
> collect the phy clocks and power control.
>
> Changes in v2: None
>
> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 26 ++++
It is preferred that you split binding doc's from driver changes.
> drivers/phy/Kconfig | 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-dp.c | 166 +++++++++++++++++++++
> 4 files changed, 200 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> create mode 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> + - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver
Please state the size of the list and order of what each entry if more than one.
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +- clock-names: from common clock binding:
> + Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
I have no idea what GRF means.
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy@ff770274 {
> + compatilble = "rockchip,rk3288-dp-phy";
> + reg = <0xff770274 4>;
> + rockchip,grf = <&grf>;
> + clocks = <&cru SCLK_EDP_24M>;
> + clock-names = "24m";
> + #phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> help
> Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> + tristate "Rockchip Display Port PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + help
> + Enable this to support the Rockchip Display Port PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12 0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN BIT(21)
> +#define DP_PHY_SIDDQ_ON 0
> +#define DP_PHY_SIDDQ_OFF BIT(5)
> +
> +struct rockchip_dp_phy {
> + struct device *dev;
> + struct regmap *grf;
> + void __iomem *regs;
> + struct clk *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> + int ret = 0;
> +
> + ret = clk_set_rate(dp->phy_24m, 24000000);
Do you need to do this every time? This can go in probe.
> + if (ret < 0) {
> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(dp->phy_24m);
> + if (ret < 0) {
> + dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> + clk_disable_unprepare(dp->phy_24m);
> +
> + return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> + if (enable) {
> + rockchip_dp_phy_clk_enable(dp);
> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> + } else {
> + rockchip_dp_phy_clk_disable(dp);
> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> + }
> +
> + return 0;
> +}
I would just inline all 3 of these functions. The wrappers don't
doesn't do anything, but add 2 levels of function calls.
> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> + return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> + return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {
> + .power_on = rockchip_dp_phy_power_on,
> + .power_off = rockchip_dp_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp_phy *dp;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> + if (IS_ERR(dp))
> + return -ENOMEM;
> +
> + dp->dev = dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + dp->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(dp->regs))
> + return PTR_ERR(dp->regs);
> +
> + dp->phy_24m = devm_clk_get(dev, "24m");
> + if (IS_ERR(dp->phy_24m)) {
> + dev_err(dev, "cannot get clock 24m\n");
> + return PTR_ERR(dp->phy_24m);
> + }
The binding says there are 2 clocks.
> +
> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> + if (IS_ERR(dp->grf)) {
> + dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> + return PTR_ERR(dp->grf);
> + }
> +
> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
> + GRF_EDP_REF_CLK_SEL_INTER |
> + (GRF_EDP_REF_CLK_SEL_INTER << 16));
> + if (ret != 0) {
> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> + return ret;
> + }
> +
> + phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
> + if (IS_ERR(phy)) {
> + dev_err(dev, "failed to create phy\n");
> + return PTR_ERR(phy);
> + }
> + phy_set_drvdata(phy, dp);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> + { .compatible = "rockchip,rk3288-dp-phy" },
> + {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> + .probe = rockchip_dp_phy_probe,
> + .driver = {
> + .name = "rockchip-dp-phy",
> + .of_match_table = rockchip_dp_phy_dt_ids,
> + },
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.2
>
>
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-03 05:30 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q4tnR-8fY-3@gated-at.bofh.it> |
| In reply to | #1217601 |
Hi Rob,
在 09/02/2015 09:27 PM, Rob Herring 写道:
> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>> rockchip_dp_phy_init() function, move those code to probe() method.
>> And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>> collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 26 ++++
> It is preferred that you split binding doc's from driver changes.
Okay, done.
>> drivers/phy/Kconfig | 7 +
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-rockchip-dp.c | 166 +++++++++++++++++++++
>> 4 files changed, 200 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> create mode 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> + - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> Please state the size of the list and order of what each entry if more than one.
Just like Heiko remind, I don't need the reg number anymore,
"rockchip,grf" is enough for this driver.
Anyway thanks :-)
>> +- clocks: from common clock binding: handle to dp clock.
>> + of memory mapped region.
>> +- clock-names: from common clock binding:
>> + Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> I have no idea what GRF means.
GRF is an module of our IC chip, the full name is General Register Files.
I would rather to pick some words from our TRM.
The general register file will be used to do static set by software, which
is composed of many registers for system control.
>
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy@ff770274 {
>> + compatilble = "rockchip,rk3288-dp-phy";
>> + reg = <0xff770274 4>;
>> + rockchip,grf = <&grf>;
>> + clocks = <&cru SCLK_EDP_24M>;
>> + clock-names = "24m";
>> + #phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>> help
>> Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> + tristate "Rockchip Display Port PHY Driver"
>> + depends on ARCH_ROCKCHIP && OF
>> + select GENERIC_PHY
>> + help
>> + Enable this to support the Rockchip Display Port PHY.
>> +
>> config PHY_ST_SPEAR1310_MIPHY
>> tristate "ST SPEAR1310-MIPHY driver"
>> select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
>> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
>> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
>> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
>> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
>> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12 0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN BIT(21)
>> +#define DP_PHY_SIDDQ_ON 0
>> +#define DP_PHY_SIDDQ_OFF BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> + struct device *dev;
>> + struct regmap *grf;
>> + void __iomem *regs;
>> + struct clk *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> + int ret = 0;
>> +
>> + ret = clk_set_rate(dp->phy_24m, 24000000);
> Do you need to do this every time? This can go in probe.
Yeah, it could move to probe, thanks.
>> + if (ret < 0) {
>> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = clk_prepare_enable(dp->phy_24m);
>> + if (ret < 0) {
>> + dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> + clk_disable_unprepare(dp->phy_24m);
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> + if (enable) {
>> + rockchip_dp_phy_clk_enable(dp);
>> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> + } else {
>> + rockchip_dp_phy_clk_disable(dp);
>> + writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> + }
>> +
>> + return 0;
>> +}
> I would just inline all 3 of these functions. The wrappers don't
> doesn't do anything, but add 2 levels of function calls.
After move clk_set_rate to probe, I would rather to remove those
wrappers just operate in power_on/power_off directly. :)
>
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> + return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> + return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
>> + .power_on = rockchip_dp_phy_power_on,
>> + .power_off = rockchip_dp_phy_power_off,
>> + .owner = THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct phy_provider *phy_provider;
>> + struct rockchip_dp_phy *dp;
>> + struct resource *res;
>> + struct phy *phy;
>> + int ret;
>> +
>> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> + if (IS_ERR(dp))
>> + return -ENOMEM;
>> +
>> + dp->dev = dev;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + dp->regs = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(dp->regs))
>> + return PTR_ERR(dp->regs);
>> +
>> + dp->phy_24m = devm_clk_get(dev, "24m");
>> + if (IS_ERR(dp->phy_24m)) {
>> + dev_err(dev, "cannot get clock 24m\n");
>> + return PTR_ERR(dp->phy_24m);
>> + }
> The binding says there are 2 clocks.
Oh... Document have been little bit old. I used to handle
two kinds of clocks in phy driver in v2, and take Thierry
and Heiko suggest to reduce to one clock in v3, but forget
to improved the Document at the same time.
+- clock-names: from common clock binding:
+ Required elements: "sclk_dp" "sclk_dp_24m"
should be
+- clock-names: from common clock binding:
+ Required elements: "24m"
Thanks for your point out.
>> +
>> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> + if (IS_ERR(dp->grf)) {
>> + dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> + return PTR_ERR(dp->grf);
>> + }
>> +
>> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> + GRF_EDP_REF_CLK_SEL_INTER |
>> + (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> + if (ret != 0) {
>> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
>> + if (IS_ERR(phy)) {
>> + dev_err(dev, "failed to create phy\n");
>> + return PTR_ERR(phy);
>> + }
>> + phy_set_drvdata(phy, dp);
>> +
>> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> + return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> + { .compatible = "rockchip,rk3288-dp-phy" },
>> + {}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> + .probe = rockchip_dp_phy_probe,
>> + .driver = {
>> + .name = "rockchip-dp-phy",
>> + .of_match_table = rockchip_dp_phy_dt_ids,
>> + },
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.1.2
>>
>>
>
>
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| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Date | 2015-09-03 16:00 +0200 |
| Subject | Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY |
| Message-ID | <q4Ddv-5mr-13@gated-at.bofh.it> |
| In reply to | #1218015 |
Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang: > 在 09/02/2015 09:27 PM, Rob Herring 写道: > > On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote: > >> +- clocks: from common clock binding: handle to dp clock. > >> + of memory mapped region. > >> +- clock-names: from common clock binding: > >> + Required elements: "sclk_dp" "sclk_dp_24m" > >> + > >> +- rockchip,grf: this soc should set GRF regs, so need get grf here. > > > > I have no idea what GRF means. > > GRF is an module of our IC chip, the full name is General Register Files. > I would rather to pick some words from our TRM. > > The general register file will be used to do static set by software, which > is composed of many registers for system control. The general register files are present on all Rockchip SoCs I've seen so far and really are just an aggregation of registers for settings and status indications, ranging from memory stuff, dma-controller settings, usb-phy and settings for a lot of other phys, etc. The most prevalent description in dt-bindings is currently: - rockchip,grf: phandle to the syscon managing the "general register files" Heiko -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Yakir Yang <ykk@rock-chips.com> |
|---|---|
| Date | 2015-09-01 08:10 +0200 |
| Subject | [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver |
| Message-ID | <q3MVA-6v2-17@gated-at.bofh.it> |
| In reply to | #1216602 |
After exynos_dp have been splited the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some samsung platform properties which
could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for
exynos DTS file for dp-controller.
Beside analogix_dp have provide the backward compatibility, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, separate all DTS changes to a separate patch.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/exynos5250-arndale.dts | 2 --
arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 --
arch/arm/boot/dts/exynos5250-snow.dts | 4 +---
arch/arm/boot/dts/exynos5250-spring.dts | 4 +---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 --
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +---
7 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index db3f65f..4636862 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
&dp {
status = "okay";
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index c625e71..cd424d6 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
&dp {
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 0720caa..242b621 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -244,12 +244,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
ports {
port@0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
- samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
};
&ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..7433683 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x06>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx2 6 0>;
+ hpd-gpio = <&gpx2 6 0>;
ports {
port@0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f9..b3df3c1 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -92,8 +92,6 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..b89bff5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios = <&gpx2 6 0>;
panel = <&panel>;
};
--
2.1.2
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2015-09-03 02:10 +0200 |
| Subject | Re: [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver |
| Message-ID | <q4qgh-3OK-9@gated-at.bofh.it> |
| In reply to | #1216616 |
On 01.09.2015 15:01, Yakir Yang wrote:
> After exynos_dp have been splited the common IP code into analogix_dp driver,
s/splited/split/
> the analogix_dp driver have deprecated some samsung platform properties which
s/samsung/Samsung/
> could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for
s/dynamic/dynamically/
> exynos DTS file for dp-controller.
/exynos/Exynos/
>
> Beside analogix_dp have provide the backward compatibility, so there are no
> bisectability break that make this change in a separate patch.
It took me some time to figure out the meaning of this sentence... Did
you want to say that backward compatibility is fully preserved?
You are removing samsung,dynamic-range and samsung,ycbcr-coeff. I would
assume that now:
1. on all these board these values would be parsed from EDID/MODE/DPCD
message?
2. everything would work as previously?
Am I understanding it correctly?
The patch itself looks good.
Best regards,
Krzysztof
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Krzysztof suggest, separate all DTS changes to a separate patch.
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/boot/dts/exynos5250-arndale.dts | 2 --
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 --
> arch/arm/boot/dts/exynos5250-snow.dts | 4 +---
> arch/arm/boot/dts/exynos5250-spring.dts | 4 +---
> arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
> arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 --
> arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +---
> 7 files changed, 4 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
> index db3f65f..4636862 100644
> --- a/arch/arm/boot/dts/exynos5250-arndale.dts
> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
> @@ -124,8 +124,6 @@
> &dp {
> status = "okay";
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index c625e71..cd424d6 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -80,8 +80,6 @@
>
> &dp {
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
> index 0720caa..242b621 100644
> --- a/arch/arm/boot/dts/exynos5250-snow.dts
> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
> @@ -244,12 +244,10 @@
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hpd>;
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <2>;
> - samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
> + hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
>
> ports {
> port@0 {
> diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
> index c1edd6d..91881d7 100644
> --- a/arch/arm/boot/dts/exynos5250-spring.dts
> +++ b/arch/arm/boot/dts/exynos5250-spring.dts
> @@ -74,12 +74,10 @@
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hpd_gpio>;
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <1>;
> - samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
> + hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
> };
>
> &ehci {
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 8f4d76c..7433683 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -148,12 +148,10 @@
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hpd_gpio>;
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x06>;
> samsung,lane-count = <2>;
> - samsung,hpd-gpio = <&gpx2 6 0>;
> + hpd-gpio = <&gpx2 6 0>;
>
> ports {
> port@0 {
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index 98871f9..b3df3c1 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -92,8 +92,6 @@
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hpd>;
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> index 7d5b386..b89bff5 100644
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> @@ -142,12 +142,10 @@
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hpd_gpio>;
> samsung,color-space = <0>;
> - samsung,dynamic-range = <0>;
> - samsung,ycbcr-coeff = <0>;
> samsung,color-depth = <1>;
> samsung,link-rate = <0x0a>;
> samsung,lane-count = <2>;
> - samsung,hpd-gpio = <&gpx2 6 0>;
> + hpd-gpios = <&gpx2 6 0>;
> panel = <&panel>;
> };
>
>
--
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