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[PATCH 0/2] adds quirk SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

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  [PATCH 0/2] adds quirk SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN Suneel Garapati <suneel.garapati@xilinx.com> - 2015-06-09 09:50 +0200
    Re: [PATCH 1/2] drivers: mmc: add quirk  SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN Jaehoon Chung <jh80.chung@samsung.com> - 2015-06-09 10:50 +0200

#1161102 — [PATCH 0/2] adds quirk SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

This quirk will support controllers whose clock divider zero is broken
and if the calculation results to zero, forcing the divider to next value.
This is tested on zynq ep108 and enables support for UHS cards where formatting
cards fail. Added few quirks to arasan platform driver as the base clock reported in
registers is broken and preset values are broken too and tested on zynq ep108
platform. max-frequency devicetree parameter is alternative to get upper limit .

Suneel Garapati (2):
  drivers: mmc: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN
  drivers: mmc: add quirks for broken clock base

 drivers/mmc/host/sdhci-of-arasan.c | 3 +++
 drivers/mmc/host/sdhci.c           | 4 ++++
 drivers/mmc/host/sdhci.h           | 2 ++
 3 files changed, 9 insertions(+)

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2.1.2
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#1161133 — Re: [PATCH 1/2] drivers: mmc: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN

Hi,

On 06/09/2015 04:31 PM, Suneel Garapati wrote:
> adds quirk for controllers whose clock divider zero is broken,
> sdhci_set_clock function will incorporate this modification.
> 
> Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
> ---
>  drivers/mmc/host/sdhci.c | 4 ++++
>  drivers/mmc/host/sdhci.h | 2 ++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 1b4861d..087327e 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1210,6 +1210,10 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> 			}
> 			real_div = div;
> 			div >>= 1;
> +			if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
> +				&& !div && host->max_clk <= 25000000) {
> +				div = 1;
> +			}

I can't understand fully. how can it be broken for divider zero?
When formatting error is occurred, do you check really clock value?
I think your patch looks like just hard-coding for control clock.

Best Regards,
Jaehoon Chung

> 		}
> 	} else {
> 		/* Version 2.00 divisors must be a power of 2. */
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 5521d29..67046ca 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -409,6 +409,8 @@ struct sdhci_host {
>  #define SDHCI_QUIRK2_SUPPORT_SINGLE			(1<<13)
>  /* Controller broken with using ACMD23 */
>  #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
> +/* Broken Clock divider zero in controller */
> +#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
> 
> 	int irq;		/* Device IRQ */
> 	void __iomem *ioaddr;	/* Mapped address */
> --
> 2.1.2
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