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[PATCH RESEND 0/2] mtd: nand: pxa3xx-nand: fixes

Started byRobert Jarzmik <robert.jarzmik@free.fr>
First post2015-08-19 20:40 +0200
Last post2015-08-20 06:10 +0200
Articles 5 — 3 participants

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  [PATCH RESEND 0/2] mtd: nand: pxa3xx-nand: fixes Robert Jarzmik <robert.jarzmik@free.fr> - 2015-08-19 20:40 +0200
    [PATCH RESEND 2/2] mtd: nand: pxa3xx-nand: fix random command timeouts Robert Jarzmik <robert.jarzmik@free.fr> - 2015-08-19 20:40 +0200
      Re: [PATCH RESEND 2/2] mtd: nand: pxa3xx-nand: fix random command timeouts Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> - 2015-08-19 23:30 +0200
    Re: [PATCH RESEND 0/2] mtd: nand: pxa3xx-nand: fixes Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> - 2015-08-19 23:20 +0200
      Re: [PATCH RESEND 0/2] mtd: nand: pxa3xx-nand: fixes Brian Norris <computersforpeace@gmail.com> - 2015-08-20 06:10 +0200

#1209981 — [PATCH RESEND 0/2] mtd: nand: pxa3xx-nand: fixes

FromRobert Jarzmik <robert.jarzmik@free.fr>
Date2015-08-19 20:40 +0200
Subject[PATCH RESEND 0/2] mtd: nand: pxa3xx-nand: fixes
Message-ID<pZgrf-5Fj-7@gated-at.bofh.it>
Hi Brian,

As promised, here are the remaining fixes I have on pxa3xx-nand I'd like you to
queue up. The other changes I have submitted are under review and not of "fixes" type.

Cheers.

--
Robert

Robert Jarzmik (2):
  mtd: nand: pxa3xx_nand: fix early spurious interrupt
  mtd: nand: pxa3xx-nand: fix random command timeouts

 drivers/mtd/nand/pxa3xx_nand.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

-- 
2.1.4

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#1209982 — [PATCH RESEND 2/2] mtd: nand: pxa3xx-nand: fix random command timeouts

FromRobert Jarzmik <robert.jarzmik@free.fr>
Date2015-08-19 20:40 +0200
Subject[PATCH RESEND 2/2] mtd: nand: pxa3xx-nand: fix random command timeouts
Message-ID<pZgrg-5Fj-17@gated-at.bofh.it>
In reply to#1209981
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read after
an erase.

The issue is that in the interrupt handler, the status bits are cleared
after the new command is issued. There is a small temporal window where
this happens :
 - the previous command has set the command done bit
 - the ready for a command bit is set
 - the handler submits the next command
   - just then, the command completes, and the command done bit is still
     set
 - the handler clears the "previous" command done bit
 - the handler exits

In this flow, the "command done" of the next command will never trigger
a new interrupt to finish the status command, as it was cleared for both
commands.

Fix this by clearing the status bit before submitting a new command.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/pxa3xx_nand.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d1a4c336de1d..d6c696798811 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -675,8 +675,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 		is_ready = 1;
 	}
 
+	/*
+	 * Clear all status bit before issuing the next command, which
+	 * can and will alter the status bits and will deserve a new
+	 * interrupt on its own. This lets the controller exit the IRQ
+	 */
+	nand_writel(info, NDSR, status);
+
 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(info, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
 		info->state = STATE_CMD_HANDLE;
 
@@ -697,8 +703,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}
 
-	/* clear NDSR to let the controller exit the IRQ */
-	nand_writel(info, NDSR, status);
 	if (is_completed)
 		complete(&info->cmd_complete);
 	if (is_ready)
-- 
2.1.4

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#1210031 — Re: [PATCH RESEND 2/2] mtd: nand: pxa3xx-nand: fix random command timeouts

FromEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Date2015-08-19 23:30 +0200
SubjectRe: [PATCH RESEND 2/2] mtd: nand: pxa3xx-nand: fix random command timeouts
Message-ID<pZj5N-15x-13@gated-at.bofh.it>
In reply to#1209982
On 19 August 2015 at 15:30, Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> When 2 commands are submitted in a row, and the second is very quick,
> the completion of the second command might never come. This happens
> especially if the second command is quick, such as a status read after
> an erase.
>
> The issue is that in the interrupt handler, the status bits are cleared
> after the new command is issued. There is a small temporal window where
> this happens :
>  - the previous command has set the command done bit
>  - the ready for a command bit is set
>  - the handler submits the next command
>    - just then, the command completes, and the command done bit is still
>      set
>  - the handler clears the "previous" command done bit
>  - the handler exits
>
> In this flow, the "command done" of the next command will never trigger
> a new interrupt to finish the status command, as it was cleared for both
> commands.
>
> Fix this by clearing the status bit before submitting a new command.
>
> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
> ---
>  drivers/mtd/nand/pxa3xx_nand.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index d1a4c336de1d..d6c696798811 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -675,8 +675,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
>                 is_ready = 1;
>         }
>
> +       /*
> +        * Clear all status bit before issuing the next command, which
> +        * can and will alter the status bits and will deserve a new
> +        * interrupt on its own. This lets the controller exit the IRQ
> +        */
> +       nand_writel(info, NDSR, status);
> +

Actually, the comment I had in mind was more about why
we *cannot* clear the NDSR register before waking the
IRQ thread.

But this is a nitpick: I don't care much :-)

>         if (status & NDSR_WRCMDREQ) {
> -               nand_writel(info, NDSR, NDSR_WRCMDREQ);
>                 status &= ~NDSR_WRCMDREQ;
>                 info->state = STATE_CMD_HANDLE;
>
> @@ -697,8 +703,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
>                         nand_writel(info, NDCB0, info->ndcb3);
>         }
>
> -       /* clear NDSR to let the controller exit the IRQ */
> -       nand_writel(info, NDSR, status);
>         if (is_completed)
>                 complete(&info->cmd_complete);
>         if (is_ready)
> --
> 2.1.4
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/



-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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#1210026

FromEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Date2015-08-19 23:20 +0200
Message-ID<pZiW6-U7-1@gated-at.bofh.it>
In reply to#1209981
On 19 August 2015 at 15:30, Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> Hi Brian,
>
> As promised, here are the remaining fixes I have on pxa3xx-nand I'd like you to
> queue up. The other changes I have submitted are under review and not of "fixes" type.
>
> Cheers.
>
> --
> Robert
>
> Robert Jarzmik (2):
>   mtd: nand: pxa3xx_nand: fix early spurious interrupt
>   mtd: nand: pxa3xx-nand: fix random command timeouts
>

For both patches:

Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

I tested this on Armada 370:

Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

-- 
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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#1210133

FromBrian Norris <computersforpeace@gmail.com>
Date2015-08-20 06:10 +0200
Message-ID<pZpkS-1Os-7@gated-at.bofh.it>
In reply to#1210026
On Wed, Aug 19, 2015 at 06:18:57PM -0300, Ezequiel Garcia wrote:
> On 19 August 2015 at 15:30, Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> > Hi Brian,
> >
> > As promised, here are the remaining fixes I have on pxa3xx-nand I'd like you to
> > queue up. The other changes I have submitted are under review and not of "fixes" type.
> >
> > Cheers.
> >
> > --
> > Robert
> >
> > Robert Jarzmik (2):
> >   mtd: nand: pxa3xx_nand: fix early spurious interrupt
> >   mtd: nand: pxa3xx-nand: fix random command timeouts
> >
> 
> For both patches:
> 
> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> 
> I tested this on Armada 370:
> 
> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Pushed both to l2-mtd.git, with Ezequiel's tags. Thanks for collecting
the patches, testing, and reviewing.

Brian
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