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| Started by | Pi-Cheng Chen <pi-cheng.chen@linaro.org> |
|---|---|
| First post | 2015-08-17 11:30 +0200 |
| Last post | 2015-08-17 11:30 +0200 |
| Articles | 3 — 1 participant |
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[RESEND PATCH 0/3 v6] Add Mediatek MT8173 cpufreq driver Pi-Cheng Chen <pi-cheng.chen@linaro.org> - 2015-08-17 11:30 +0200
[RESEND PATCH 3/3 v6] arm64: dts: mt8173: mt8173-evb: Add mt8173 cpufreq driver support Pi-Cheng Chen <pi-cheng.chen@linaro.org> - 2015-08-17 11:30 +0200
[RESEND PATCH 1/3 v6] dt-bindings: mediatek: Add MT8173 CPU DVFS clock bindings Pi-Cheng Chen <pi-cheng.chen@linaro.org> - 2015-08-17 11:30 +0200
| From | Pi-Cheng Chen <pi-cheng.chen@linaro.org> |
|---|---|
| Date | 2015-08-17 11:30 +0200 |
| Subject | [RESEND PATCH 0/3 v6] Add Mediatek MT8173 cpufreq driver |
| Message-ID | <pYoTU-3bm-7@gated-at.bofh.it> |
MT8173 is a ARMv8 based SoC with 2 clusters. All CPUs in a single cluster share the same power and clock domain. This series tries to add cpufreq support for MT8173 SoC. The v6 of this series is resent with Acks added. changes in v6: - Move clock and regulator consumer properties document to the device tree bindings documents of MT8173 CPU DVFS clock driver - Add change log to describe what is implemented in the MT8173 cpufreq driver - Add missed rcu_read_unlock() in the error path - Move of_init_opp_table() call to make sure all required hardware resources are already there before it is called - Add comments to describe why both platform driver and deivce registration codes are put in the initcall function - Use the term "voltage tracking" instead of "voltage trace" according to an internal SoC document changes in v5: - Move resource allocation code from init() into probe() and remove some unused functions due to this change - Fix descriptions for device tree binding document - Address review comments for last version - Register CPU cooling device Changes in v4: - Add bindings for MT8173 cpufreq driver - Move OPP table back into device tree - Address comments for last version Changes in v3: - Implement MT8173 specific standalone cpufreq driver instead of using cpufreq-dt driver - Define OPP table in the driver source code until new OPP binding is ready Changes in v2: - Add intermediate frequency support in cpufreq-dt driver - Use voltage scaling code of cpufreq-dt for little cluster instead of implementaion in notifier of mtk-cpufreq driver - Code refinement for mtk-cpufreq driver Pi-Cheng Chen (3): dt-bindings: mediatek: Add MT8173 CPU DVFS clock bindings cpufreq: mediatek: Add MT8173 cpufreq driver arm64: dts: mt8173: Add mt8173 cpufreq driver support .../devicetree/bindings/clock/mt8173-cpu-dvfs.txt | 83 ++++ arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 + arch/arm64/boot/dts/mediatek/mt8173.dtsi | 64 +++ drivers/cpufreq/Kconfig.arm | 7 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/mt8173-cpufreq.c | 524 +++++++++++++++++++++ 6 files changed, 697 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt create mode 100644 drivers/cpufreq/mt8173-cpufreq.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Pi-Cheng Chen <pi-cheng.chen@linaro.org> |
|---|---|
| Date | 2015-08-17 11:30 +0200 |
| Subject | [RESEND PATCH 3/3 v6] arm64: dts: mt8173: mt8173-evb: Add mt8173 cpufreq driver support |
| Message-ID | <pYoTV-3bm-29@gated-at.bofh.it> |
| In reply to | #1208496 |
This patch adds the required properties in device tree to enable MT8173
cpufreq driver.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
It is based on the top of MT8173 SoC maintainer's tree:
https://github.com/mbgg/linux-mediatek.git v4.2-next/arm64
commit id: e26945245e414eff42ee1ffeaedf198911bf1d77
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 64 +++++++++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index dc4a3e2..ddb1dc1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -261,6 +261,24 @@
};
};
+&cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 359b8b6..47a443d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -53,6 +53,22 @@
reg = <0x000>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points = <
+ 507000 859000
+ 702000 908000
+ 1001000 983000
+ 1105000 1009000
+ 1183000 1028000
+ 1404000 1083000
+ 1508000 1109000
+ 1573000 1125000
+ >;
+ #cooling-cells = <2>;
+ #cooling-min-level = <0>;
+ #cooling-max-level = <7>;
};
cpu1: cpu@1 {
@@ -61,6 +77,22 @@
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points = <
+ 507000 859000
+ 702000 908000
+ 1001000 983000
+ 1105000 1009000
+ 1183000 1028000
+ 1404000 1083000
+ 1508000 1109000
+ 1573000 1125000
+ >;
+ #cooling-cells = <2>;
+ #cooling-min-level = <0>;
+ #cooling-max-level = <7>;
};
cpu2: cpu@100 {
@@ -69,6 +101,22 @@
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points = <
+ 507000 828000
+ 702000 867000
+ 1001000 927000
+ 1209000 968000
+ 1404000 1007000
+ 1612000 1049000
+ 1807000 1089000
+ 1989000 1125000
+ >;
+ #cooling-cells = <2>;
+ #cooling-min-level = <0>;
+ #cooling-max-level = <7>;
};
cpu3: cpu@101 {
@@ -77,6 +125,22 @@
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points = <
+ 507000 828000
+ 702000 867000
+ 1001000 927000
+ 1209000 968000
+ 1404000 1007000
+ 1612000 1049000
+ 1807000 1089000
+ 1989000 1125000
+ >;
+ #cooling-cells = <2>;
+ #cooling-min-level = <0>;
+ #cooling-max-level = <7>;
};
idle-states {
--
1.9.1
--
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| From | Pi-Cheng Chen <pi-cheng.chen@linaro.org> |
|---|---|
| Date | 2015-08-17 11:30 +0200 |
| Subject | [RESEND PATCH 1/3 v6] dt-bindings: mediatek: Add MT8173 CPU DVFS clock bindings |
| Message-ID | <pYoTV-3bm-31@gated-at.bofh.it> |
| In reply to | #1208496 |
This patch adds the clock and regulator consumer properties part of
document for CPU DVFS clocks on Mediatek MT8173 SoC.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
.../devicetree/bindings/clock/mt8173-cpu-dvfs.txt | 83 ++++++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
diff --git a/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt b/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
new file mode 100644
index 0000000..52b457c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
@@ -0,0 +1,83 @@
+Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+ "cpu" - The multiplexer for clock input of CPU cluster.
+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
+ source (usually MAINPLL) when the original CPU PLL is under
+ transition and not stable yet.
+ Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ generic clock consumer properties.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+ needs to do "voltage tracking" to step by step scale up/down Vproc and
+ Vsram to fit SoC specific needs. When absent, the voltage scaling
+ flow is handled by hardware, hence no software "voltage tracking" is
+ needed.
+
+Example:
+--------
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ &cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
+
+ &cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
--
1.9.1
--
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