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| Started by | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| First post | 2015-08-11 05:50 +0200 |
| Last post | 2015-08-17 05:40 +0200 |
| Articles | 3 — 3 participants |
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[PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi <cw00.choi@samsung.com> - 2015-08-11 05:50 +0200
Re: [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-08-17 04:20 +0200
Re: [3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Pankaj Dubey <pankaj.dubey@samsung.com> - 2015-08-17 05:40 +0200
| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2015-08-11 05:50 +0200 |
| Subject | [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC |
| Message-ID | <pW8Jz-1BB-1@gated-at.bofh.it> |
This patch add the uart2 devicetree node for Exynos3250 SoC.
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 5ab81c39e2c9..eac1d21c10d4 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -120,6 +120,13 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 2db99433e17f..02f3250766c9 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
};
cpus {
@@ -435,6 +436,17 @@
status = "disabled";
};
+ serial_2: serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c@13860000 {
#address-cells = <1>;
#size-cells = <0>;
--
1.8.5.5
--
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2015-08-17 04:20 +0200 |
| Message-ID | <pYibL-1Tp-9@gated-at.bofh.it> |
| In reply to | #1204721 |
On 11.08.2015 12:46, Chanwoo Choi wrote: > This patch add the uart2 devicetree node for Exynos3250 SoC. "This patch adds the UART2 Device Tree node..." > > Cc: Kukjin Kim <kgene@kernel.org> > Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++ > arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++ > 2 files changed, 19 insertions(+) Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Pankaj Dubey <pankaj.dubey@samsung.com> |
|---|---|
| Date | 2015-08-17 05:40 +0200 |
| Subject | Re: [3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC |
| Message-ID | <pYjrb-3Ie-7@gated-at.bofh.it> |
| In reply to | #1204721 |
Hi Chanwoo,
Similar patch was posted here[1].
[1]:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/291023.html
Thanks,
Pankaj Dubey
On Tuesday 11 August 2015 09:16 AM, Chanwoo Choi wrote:
> This patch add the uart2 devicetree node for Exynos3250 SoC.
>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> ---
> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
> arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> index 5ab81c39e2c9..eac1d21c10d4 100644
> --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> @@ -120,6 +120,13 @@
> samsung,pin-drv = <0>;
> };
>
> + uart2_data: uart2-data {
> + samsung,pins = "gpa1-0", "gpa1-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> i2c3_bus: i2c3-bus {
> samsung,pins = "gpa1-2", "gpa1-3";
> samsung,pin-function = <3>;
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 2db99433e17f..02f3250766c9 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -42,6 +42,7 @@
> i2c7 = &i2c_7;
> serial0 = &serial_0;
> serial1 = &serial_1;
> + serial2 = &serial_2;
> };
>
> cpus {
> @@ -435,6 +436,17 @@
> status = "disabled";
> };
>
> + serial_2: serial@13820000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x13820000 0x100>;
> + interrupts = <0 111 0>;
> + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_data>;
> + status = "disabled";
> + };
> +
> i2c_0: i2c@13860000 {
> #address-cells = <1>;
> #size-cells = <0>;
>
--
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