Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1200862 > unrolled thread

[PATCH v2 0/8] ARCv2 port to Linux - (C) perf

Back to article view | Back to linux.kernel

Contents

  [PATCH v2 0/8] ARCv2 port to Linux - (C) perf Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2015-08-05 17:20 +0200
    [PATCH v2 1/8] ARC: perf: support RAW events Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2015-08-05 17:20 +0200
    [PATCH v2 4/8] ARCv2: perf: Support sampling events using overflow interrupts Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2015-08-05 17:20 +0200
      Re: [PATCH v2 4/8] ARCv2: perf: Support sampling events using  overflow interrupts Peter Zijlstra <peterz@infradead.org> - 2015-08-19 00:20 +0200
    Re: [PATCH v2 0/8] ARCv2 port to Linux - (C) perf Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2015-08-10 10:30 +0200
    Re: [arc-linux-dev] [PATCH v2 0/8] ARCv2 port to Linux - (C) perf Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-08-14 09:50 +0200

#1200862 — [PATCH v2 0/8] ARCv2 port to Linux - (C) perf

Hi Peter,

This mini-series adds perf support for ARCv2 based cores, which brings in
overflow interupts and SMP. Additionally now raw events are supported as well.

Please review !

Compared to v1 this series has:
 [1] Addressed review comments
 [2] More verbose commit messages and comments in sources
 [3] Minor cosmetics

Thanks,
Alexey


Alexey Brodkin (6):
  ARC: perf: support RAW events
  ARCv2: perf: implement "event_set_period" for future use with
    interrupts
  ARCv2: perf: Support sampling events using overflow interrupts
  ARCv2: perf: set usable max period as a half of real max period
  ARCv2: perf: implement exclusion of event counting in user or kernel
    mode
  ARCv2: perf: SMP support

Vineet Gupta (2):
  ARC: perf: cap the number of counters to hardware max of 32
  ARCv2: perf: Finally introduce HS perf unit

 .../devicetree/bindings/arc/archs-pct.txt          |  17 +
 MAINTAINERS                                        |   2 +-
 arch/arc/include/asm/perf_event.h                  |  24 +-
 arch/arc/kernel/perf_event.c                       | 350 ++++++++++++++++++---
 4 files changed, 345 insertions(+), 48 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arc/archs-pct.txt

-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [next] | [standalone]

#1200867 — [PATCH v2 1/8] ARC: perf: support RAW events

To run perf against raw event user may issue following command:
 -------------->-------------
 # perf stat -e r6372756e ls -la /proc > /dev/null

  Performance counter stats for 'ls -la /proc':

            7336905      r6372756e

        0.085494733 seconds time elapsed
 -------------->-------------

"-e rXXX" is indication of raw event to count.
XXX is 64-bit ASCII value.
0x6372756e = crun (in ASCII)

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---

Compared to v1:
 [1] Swapping of event names moved to probe routine so now we're closer to
     real raw event in terms of accepting exactly what user entered.
 [2] Added comment in sources that explains logic for swapping etc.
 [3] Cosmetics

 arch/arc/include/asm/perf_event.h |  3 ++
 arch/arc/kernel/perf_event.c      | 78 +++++++++++++++++++++++++++++++++------
 2 files changed, 69 insertions(+), 12 deletions(-)

diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h
index 2b8880e..ea43477 100644
--- a/arch/arc/include/asm/perf_event.h
+++ b/arch/arc/include/asm/perf_event.h
@@ -15,6 +15,9 @@
 /* real maximum varies per CPU, this is the maximum supported by the driver */
 #define ARC_PMU_MAX_HWEVENTS	64
 
+/* Max number of countable events that CPU may have */
+#define ARC_PERF_MAX_EVENTS	256
+
 #define ARC_REG_CC_BUILD	0xF6
 #define ARC_REG_CC_INDEX	0x240
 #define ARC_REG_CC_NAME0	0x241
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index 1287388..ae4a921 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -22,8 +22,10 @@ struct arc_pmu {
 	struct pmu	pmu;
 	int		counter_size;	/* in bits */
 	int		n_counters;
+	int		n_events;
 	unsigned long	used_mask[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS)];
 	int		ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
+	u64             raw_events[ARC_PERF_MAX_EVENTS];
 };
 
 struct arc_callchain_trace {
@@ -136,6 +138,18 @@ static int arc_pmu_cache_event(u64 config)
 	return ret;
 }
 
+static int arc_pmu_raw_event(u64 config)
+{
+	int i;
+
+	for (i = 0; i < arc_pmu->n_events; i++) {
+		if (config == arc_pmu->raw_events[i])
+			return i;
+	}
+
+	return -ENOENT;
+}
+
 /* initializes hw_perf_event structure if event is supported */
 static int arc_pmu_event_init(struct perf_event *event)
 {
@@ -159,6 +173,14 @@ static int arc_pmu_event_init(struct perf_event *event)
 			return ret;
 		hwc->config = arc_pmu->ev_hw_idx[ret];
 		return 0;
+
+	case PERF_TYPE_RAW:
+		ret = arc_pmu_raw_event(event->attr.config);
+		if (ret < 0)
+			return ret;
+		hwc->config |= ret;
+		return 0;
+
 	default:
 		return -ENOENT;
 	}
@@ -270,15 +292,15 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
 	struct arc_reg_cc_build cc_bcr;
 	int i, j;
 
-	union cc_name {
-		struct {
-			uint32_t word0, word1;
-			char sentinel;
-		} indiv;
-		char str[9];
+	struct cc_name {
+		union {
+			uint32_t word[2];
+			u64	 dword;
+			char	 str[8];
+		} u;
+		char sentinel[8];
 	} cc_name;
 
-
 	READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
 	if (!pct_bcr.v) {
 		pr_err("This core does not have performance counters!\n");
@@ -288,6 +310,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
 
 	READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
 	BUG_ON(!cc_bcr.v); /* Counters exist but No countable conditions ? */
+	BUG_ON(cc_bcr.c > ARC_PERF_MAX_EVENTS);
 
 	arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
 	if (!arc_pmu)
@@ -299,23 +322,54 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
 	pr_info("ARC perf\t: %d counters (%d bits), %d countable conditions\n",
 		arc_pmu->n_counters, arc_pmu->counter_size, cc_bcr.c);
 
-	cc_name.str[8] = 0;
+	arc_pmu->n_events = cc_bcr.c;
+
 	for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++)
 		arc_pmu->ev_hw_idx[i] = -1;
 
+	cc_name.sentinel[0] = '\0';
+
 	/* loop thru all available h/w condition indexes */
 	for (j = 0; j < cc_bcr.c; j++) {
+		u64 name;
+
 		write_aux_reg(ARC_REG_CC_INDEX, j);
-		cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
-		cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
+		cc_name.u.word[0] = read_aux_reg(ARC_REG_CC_NAME0);
+		cc_name.u.word[1] = read_aux_reg(ARC_REG_CC_NAME1);
+
+		/*
+		 * condition name caching for raw events
+		 *
+		 * In PCT register CC_NAME{0,1} event name string[] is saved
+		 * from LSB side:
+		 * e.g. cycles corresponds to "crun" and is saved as 0x6e757263
+		 *						       n u r c
+		 * However in perf cmdline they are specified in human order as
+		 * r6372756e
+		 *
+		 * Thus save a 64bit swapped value for quick cross check at the
+		 * time of raw event request, which will give in example above:
+		 * __swab64(0x000000006e757263) = 0x6372756e00000000.
+		 * And then to finally have 0x6372756e, trim the trailing zeroes
+		 */
+		name = __swab64(cc_name.u.dword);
+
+		/* Trim leading zeroes */
+		for (i = 0; i < sizeof(u64); i++)
+			if (!(name & 0xFF))
+				name = name >> 8;
+			else
+				break;
+
+		arc_pmu->raw_events[j] = name;
 
 		/* See if it has been mapped to a perf event_id */
 		for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
 			if (arc_pmu_ev_hw_map[i] &&
-			    !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
+			    !strcmp(arc_pmu_ev_hw_map[i], cc_name.u.str) &&
 			    strlen(arc_pmu_ev_hw_map[i])) {
 				pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n",
-					 i, cc_name.str, j);
+					 i, cc_name.u.str, j);
 				arc_pmu->ev_hw_idx[i] = j;
 			}
 		}
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [prev] | [next] | [standalone]

#1200868 — [PATCH v2 4/8] ARCv2: perf: Support sampling events using overflow interrupts

In times of ARC 700 performance counters didn't have support of
interrupt an so for ARC we only had support of non-sampling events.

Put simply only "perf stat" was functional.

Now with ARC HS we have support of interrupts in performance counters
which this change introduces support of.

ARC performance counters act in the following way in regard of
interrupts generation.
 [1] A counter counts starting from value set in PCT_COUNT register pair
 [2] Once counter reaches value set in PCT_INT_CNT interrupt is raised

Basic setup look like this:
 [1] PCT_COUNT = 0;
 [2] PCT_INT_CNT = __limit_value__;
 [3] Enable interrupts for that counter and let it run
 [4] Let counter reach its limit
 [5] Handle interrupt when it happens

Note that PCT HW block is build in CPU core and so ints interrupt
line (which is basically OR of all counters IRQs) is wired directly to
top-level IRQC. That means do de-assert PCT interrupt it's required to
reset IRQs from all counters that have reached their limit values.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---

Compared to v1:
 [1] Added commit message
 [2] Removed check for is_sampling_event() because we already set
     PERF_PMU_CAP_NO_INTERRUPT in probe()
 [3] Minor cosmetics

 arch/arc/include/asm/perf_event.h |   8 ++-
 arch/arc/kernel/perf_event.c      | 127 +++++++++++++++++++++++++++++++++++---
 2 files changed, 125 insertions(+), 10 deletions(-)

diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h
index ca8c414..33a6eb2 100644
--- a/arch/arc/include/asm/perf_event.h
+++ b/arch/arc/include/asm/perf_event.h
@@ -32,15 +32,19 @@
 #define ARC_REG_PCT_CONFIG	0x254
 #define ARC_REG_PCT_CONTROL	0x255
 #define ARC_REG_PCT_INDEX	0x256
+#define ARC_REG_PCT_INT_CNTL	0x25C
+#define ARC_REG_PCT_INT_CNTH	0x25D
+#define ARC_REG_PCT_INT_CTRL	0x25E
+#define ARC_REG_PCT_INT_ACT	0x25F
 
 #define ARC_REG_PCT_CONTROL_CC	(1 << 16)	/* clear counts */
 #define ARC_REG_PCT_CONTROL_SN	(1 << 17)	/* snapshot */
 
 struct arc_reg_pct_build {
 #ifdef CONFIG_CPU_BIG_ENDIAN
-	unsigned int m:8, c:8, r:6, s:2, v:8;
+	unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
 #else
-	unsigned int v:8, s:2, r:6, c:8, m:8;
+	unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
 #endif
 };
 
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index 2d95440..1a9f922 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -11,6 +11,7 @@
  *
  */
 #include <linux/errno.h>
+#include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/perf_event.h>
@@ -25,6 +26,7 @@ struct arc_pmu {
 	unsigned long	used_mask[BITS_TO_LONGS(ARC_PERF_MAX_COUNTERS)];
 	u64		max_period;
 	int		ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
+	struct perf_event *act_counter[ARC_PERF_MAX_COUNTERS];
 	u64             raw_events[ARC_PERF_MAX_EVENTS];
 };
 
@@ -153,9 +155,11 @@ static int arc_pmu_event_init(struct perf_event *event)
 	struct hw_perf_event *hwc = &event->hw;
 	int ret;
 
-	hwc->sample_period  = arc_pmu->max_period;
-	hwc->last_period = hwc->sample_period;
-	local64_set(&hwc->period_left, hwc->sample_period);
+	if (!is_sampling_event(event)) {
+		hwc->sample_period  = arc_pmu->max_period;
+		hwc->last_period = hwc->sample_period;
+		local64_set(&hwc->period_left, hwc->sample_period);
+	}
 
 	switch (event->attr.type) {
 	case PERF_TYPE_HARDWARE:
@@ -277,6 +281,17 @@ static void arc_pmu_stop(struct perf_event *event, int flags)
 	struct hw_perf_event *hwc = &event->hw;
 	int idx = hwc->idx;
 
+	/* Disable interrupt for this counter */
+	if (is_sampling_event(event)) {
+		/*
+		 * Reset interrupt flag by writing of 1. This is required
+		 * to make sure pending interrupt was not left.
+		 */
+		write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
+		write_aux_reg(ARC_REG_PCT_INT_CTRL,
+			      read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~(1 << idx));
+	}
+
 	if (!(event->hw.state & PERF_HES_STOPPED)) {
 		/* stop ARC pmu here */
 		write_aux_reg(ARC_REG_PCT_INDEX, idx);
@@ -299,6 +314,8 @@ static void arc_pmu_del(struct perf_event *event, int flags)
 	arc_pmu_stop(event, PERF_EF_UPDATE);
 	__clear_bit(event->hw.idx, arc_pmu->used_mask);
 
+	arc_pmu->act_counter[event->hw.idx] = 0;
+
 	perf_event_update_userpage(event);
 }
 
@@ -319,6 +336,20 @@ static int arc_pmu_add(struct perf_event *event, int flags)
 	}
 
 	write_aux_reg(ARC_REG_PCT_INDEX, idx);
+
+	arc_pmu->act_counter[idx] = event;
+
+	if (is_sampling_event(event)) {
+		/* Mimic full counter overflow as other arches do */
+		write_aux_reg(ARC_REG_PCT_INT_CNTL, (u32)arc_pmu->max_period);
+		write_aux_reg(ARC_REG_PCT_INT_CNTH,
+			      (arc_pmu->max_period >> 32));
+
+		/* Enable interrupt for this counter */
+		write_aux_reg(ARC_REG_PCT_INT_CTRL,
+			      read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
+	}
+
 	write_aux_reg(ARC_REG_PCT_CONFIG, 0);
 	write_aux_reg(ARC_REG_PCT_COUNTL, 0);
 	write_aux_reg(ARC_REG_PCT_COUNTH, 0);
@@ -333,11 +364,70 @@ static int arc_pmu_add(struct perf_event *event, int flags)
 	return 0;
 }
 
+#ifdef CONFIG_ISA_ARCV2
+static irqreturn_t arc_pmu_intr(int irq, void *dev)
+{
+	struct perf_sample_data data;
+	struct arc_pmu *arc_pmu = (struct arc_pmu *)dev;
+	struct pt_regs *regs;
+	int active_ints;
+	int idx;
+
+	arc_pmu_disable(&arc_pmu->pmu);
+
+	active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);
+
+	regs = get_irq_regs();
+
+	for (idx = 0; idx < arc_pmu->n_counters; idx++) {
+		struct perf_event *event = arc_pmu->act_counter[idx];
+		struct hw_perf_event *hwc;
+
+		if (!(active_ints & (1 << idx)))
+			continue;
+
+		/* Reset interrupt flag by writing of 1 */
+		write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
+
+		/*
+		 * On reset of "interrupt active" bit corresponding
+		 * "interrupt enable" bit gets automatically reset as well.
+		 * Now we need to re-enable interrupt for the counter.
+		 */
+		write_aux_reg(ARC_REG_PCT_INT_CTRL,
+			read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
+
+		hwc = &event->hw;
+
+		WARN_ON_ONCE(hwc->idx != idx);
+
+		arc_perf_event_update(event, &event->hw, event->hw.idx);
+		perf_sample_data_init(&data, 0, hwc->last_period);
+		if (!arc_pmu_event_set_period(event))
+			continue;
+
+		if (perf_event_overflow(event, &data, regs))
+			arc_pmu_stop(event, 0);
+	}
+
+	arc_pmu_enable(&arc_pmu->pmu);
+
+	return IRQ_HANDLED;
+}
+#else
+
+static irqreturn_t arc_pmu_intr(int irq, void *dev)
+{
+	return IRQ_NONE;
+}
+
+#endif /* CONFIG_ISA_ARCV2 */
+
 static int arc_pmu_device_probe(struct platform_device *pdev)
 {
 	struct arc_reg_pct_build pct_bcr;
 	struct arc_reg_cc_build cc_bcr;
-	int i, j;
+	int i, j, has_interrupts;
 	int counter_size;	/* in bits */
 
 	struct cc_name {
@@ -364,12 +454,16 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
 	if (!arc_pmu)
 		return -ENOMEM;
 
+	has_interrupts = is_isa_arcv2() ? pct_bcr.i : 0;
+
 	arc_pmu->n_counters = pct_bcr.c;
 	counter_size = 32 + (pct_bcr.s << 4);
+
 	arc_pmu->max_period = (1ULL << counter_size) - 1ULL;
 
-	pr_info("ARC perf\t: %d counters (%d bits), %d countable conditions\n",
-		arc_pmu->n_counters, counter_size, cc_bcr.c);
+	pr_info("ARC perf\t: %d counters (%d bits), %d conditions%s\n",
+		arc_pmu->n_counters, counter_size, cc_bcr.c,
+		has_interrupts ? ", [overflow IRQ support]":"");
 
 	arc_pmu->n_events = cc_bcr.c;
 
@@ -435,8 +529,25 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
 		.read		= arc_pmu_read,
 	};
 
-	/* ARC 700 PMU does not support sampling events */
-	arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
+	if (has_interrupts) {
+		int irq = platform_get_irq(pdev, 0);
+
+		if (irq < 0) {
+			pr_err("Cannot get IRQ number for the platform\n");
+			return -ENODEV;
+		}
+
+		ret = devm_request_irq(&pdev->dev, irq, arc_pmu_intr, 0,
+				       "arc-pmu", arc_pmu);
+		if (ret) {
+			pr_err("could not allocate PMU IRQ\n");
+			return ret;
+		}
+
+		/* Clean all pending interrupt flags */
+		write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);
+	} else
+		arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 
 	return perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
 }
-- 
2.4.3

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [prev] | [next] | [standalone]

#1209513 — Re: [PATCH v2 4/8] ARCv2: perf: Support sampling events using overflow interrupts

On Wed, Aug 05, 2015 at 06:13:30PM +0300, Alexey Brodkin wrote:
> @@ -319,6 +336,20 @@ static int arc_pmu_add(struct perf_event *event, int flags)
>  	}
>  
>  	write_aux_reg(ARC_REG_PCT_INDEX, idx);
> +
> +	arc_pmu->act_counter[idx] = event;
> +
> +	if (is_sampling_event(event)) {
> +		/* Mimic full counter overflow as other arches do */
> +		write_aux_reg(ARC_REG_PCT_INT_CNTL, (u32)arc_pmu->max_period);
> +		write_aux_reg(ARC_REG_PCT_INT_CNTH,
> +			      (arc_pmu->max_period >> 32));
> +
> +		/* Enable interrupt for this counter */
> +		write_aux_reg(ARC_REG_PCT_INT_CTRL,
> +			      read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
> +	}

*confused* pmu::add should only start on flags & PERF_EF_START, and then
we start with hwc->sample_period, not the max_period.

> +
>  	write_aux_reg(ARC_REG_PCT_CONFIG, 0);
>  	write_aux_reg(ARC_REG_PCT_COUNTL, 0);
>  	write_aux_reg(ARC_REG_PCT_COUNTH, 0);
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [prev] | [next] | [standalone]

#1203887

Hi Peter,

On Wed, 2015-08-05 at 18:13 +-0300, Alexey Brodkin wrote:
+AD4- Hi Peter,
+AD4- 
+AD4- This mini-series adds perf support for ARCv2 based cores, which brings in
+AD4- overflow interupts and SMP. Additionally now raw events are supported as well.
+AD4- 
+AD4- Please review +ACE-
+AD4- 
+AD4- Compared to v1 this series has:
+AD4-  +AFs-1+AF0- Addressed review comments
+AD4-  +AFs-2+AF0- More verbose commit messages and comments in sources
+AD4-  +AFs-3+AF0- Minor cosmetics
+AD4- 
+AD4- Thanks,
+AD4- Alexey
+AD4- 
+AD4- 
+AD4- Alexey Brodkin (6):
+AD4-   ARC: perf: support RAW events
+AD4-   ARCv2: perf: implement +ACI-event+AF8-set+AF8-period+ACI- for future use with
+AD4-     interrupts
+AD4-   ARCv2: perf: Support sampling events using overflow interrupts
+AD4-   ARCv2: perf: set usable max period as a half of real max period
+AD4-   ARCv2: perf: implement exclusion of event counting in user or kernel
+AD4-     mode
+AD4-   ARCv2: perf: SMP support
+AD4- 
+AD4- Vineet Gupta (2):
+AD4-   ARC: perf: cap the number of counters to hardware max of 32
+AD4-   ARCv2: perf: Finally introduce HS perf unit
+AD4- 
+AD4-  .../devicetree/bindings/arc/archs-pct.txt          +AHw-  17 +-
+AD4-  MAINTAINERS                                        +AHw-   2 +--
+AD4-  arch/arc/include/asm/perf+AF8-event.h                  +AHw-  24 +--
+AD4-  arch/arc/kernel/perf+AF8-event.c                       +AHw- 350 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+----
+AD4-  4 files changed, 345 insertions(+-), 48 deletions(-)
+AD4-  create mode 100644 Documentation/devicetree/bindings/arc/archs-pct.txt
+AD4- 

Any chance for this series respin to be reviewed sometime soon?

-Alexey--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [prev] | [next] | [standalone]

#1207381 — Re: [arc-linux-dev] [PATCH v2 0/8] ARCv2 port to Linux - (C) perf

On Wednesday 05 August 2015 08:44 PM, Alexey Brodkin wrote:
> Hi Peter,
>
> This mini-series adds perf support for ARCv2 based cores, which brings in
> overflow interupts and SMP. Additionally now raw events are supported as well.
>
> Please review !
>
> Compared to v1 this series has:
>  [1] Addressed review comments
>  [2] More verbose commit messages and comments in sources
>  [3] Minor cosmetics
>
> Thanks,
> Alexey

Hi Peter,

Can u please skim thru these any time soon. Merge window is drawing nearer and it
would be nice to have perf for ARCv2 based cores in there.

Thx,
-Vineet
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web