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Groups > linux.kernel > #1204758 > unrolled thread
| Started by | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| First post | 2015-08-11 07:40 +0200 |
| Last post | 2015-08-13 09:20 +0200 |
| Articles | 4 — 2 participants |
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[PATCH 0/3] ARM: sun6i: Support Security System crypto engine Chen-Yu Tsai <wens@csie.org> - 2015-08-11 07:40 +0200
[PATCH 3/3] ARM: dts: sun6i: Add security system crypto engine clock and device nodes Chen-Yu Tsai <wens@csie.org> - 2015-08-11 07:40 +0200
[PATCH 1/3] crypto: sunxi-ss: Document optional reset control bindings Chen-Yu Tsai <wens@csie.org> - 2015-08-11 07:40 +0200
Re: [PATCH 0/3] ARM: sun6i: Support Security System crypto engine Herbert Xu <herbert@gondor.apana.org.au> - 2015-08-13 09:20 +0200
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-08-11 07:40 +0200 |
| Subject | [PATCH 0/3] ARM: sun6i: Support Security System crypto engine |
| Message-ID | <pWas2-48U-7@gated-at.bofh.it> |
Hi everyone,
This series enables support for the crypto engine found in sun6i, or
Allwinner A31/A31s SoCs. The crypto engine is the same hardware as on
earlier sun4i/sun7i (A10/A20), with the only difference being the reset
control is separated out of the clock gate control.
The same hardware is also available on the A33, but not the A23. Support
for this requires additions to the clock driver, and will be submitted
separately once things are clear on how to proceed. I already have a
proof of concept working.
Patch 1 adds an optional reset control property to the sunxi-ss binding.
Patch 2 adds optional reset control support to the sunxi-ss driver.
Patch 3 enables the crypto engine on sun6i, by adding the module clock and
device node.
Regards
ChenYu
Chen-Yu Tsai (3):
crypto: sunxi-ss: Document optional reset control bindings
crypto: sunxi-ss: Add optional reset control support
ARM: dts: sun6i: Add security system crypto engine clock and device
nodes
.../devicetree/bindings/crypto/sun4i-ss.txt | 4 ++++
arch/arm/boot/dts/sun6i-a31.dtsi | 18 ++++++++++++++++++
drivers/crypto/sunxi-ss/sun4i-ss-core.c | 22 ++++++++++++++++++++++
drivers/crypto/sunxi-ss/sun4i-ss.h | 2 ++
4 files changed, 46 insertions(+)
--
2.5.0
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-08-11 07:40 +0200 |
| Subject | [PATCH 3/3] ARM: dts: sun6i: Add security system crypto engine clock and device nodes |
| Message-ID | <pWas2-48U-11@gated-at.bofh.it> |
| In reply to | #1204758 |
A31/A31s have the same "Security System" crypto engine as A10/A20,
but with a separate reset control.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 39953e76bbfc..7afb80f07dad 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -346,6 +346,14 @@
"mmc3_sample";
};
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "ss";
+ };
+
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -882,6 +890,16 @@
#size-cells = <0>;
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 5>;
+ reset-names = "ahb";
+ };
+
timer@01c60000 {
compatible = "allwinner,sun6i-a31-hstimer",
"allwinner,sun7i-a20-hstimer";
--
2.5.0
--
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-08-11 07:40 +0200 |
| Subject | [PATCH 1/3] crypto: sunxi-ss: Document optional reset control bindings |
| Message-ID | <pWas2-48U-17@gated-at.bofh.it> |
| In reply to | #1204758 |
Later Allwinner SoCs split out the reset controls for individual modules
out of the clock gate controls. The "Security System" crypto engine is
no different.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
index 1e02d177fea6..5d38e9b7033f 100644
--- a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
+++ b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
@@ -9,6 +9,10 @@ Required properties:
* "ahb" : AHB gating clock
* "mod" : SS controller clock
+Optional properties:
+ - resets : phandle + reset specifier pair
+ - reset-names : must contain "ahb"
+
Example:
crypto: crypto-engine@01c15000 {
compatible = "allwinner,sun4i-a10-crypto";
--
2.5.0
--
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| From | Herbert Xu <herbert@gondor.apana.org.au> |
|---|---|
| Date | 2015-08-13 09:20 +0200 |
| Message-ID | <pWUXU-4He-21@gated-at.bofh.it> |
| In reply to | #1204758 |
On Tue, Aug 11, 2015 at 01:32:54PM +0800, Chen-Yu Tsai wrote: > Hi everyone, > > This series enables support for the crypto engine found in sun6i, or > Allwinner A31/A31s SoCs. The crypto engine is the same hardware as on > earlier sun4i/sun7i (A10/A20), with the only difference being the reset > control is separated out of the clock gate control. > > The same hardware is also available on the A33, but not the A23. Support > for this requires additions to the clock driver, and will be submitted > separately once things are clear on how to proceed. I already have a > proof of concept working. > > > Patch 1 adds an optional reset control property to the sunxi-ss binding. > > Patch 2 adds optional reset control support to the sunxi-ss driver. > > Patch 3 enables the crypto engine on sun6i, by adding the module clock and > device node. All applied. Thanks. -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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