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RE: [PATCH 1/2] KVM: x86: set TMR when the interrupt is accepted

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  RE: [PATCH 1/2] KVM: x86: set TMR when the interrupt is accepted "Zhang, Yang Z" <yang.z.zhang@intel.com> - 2015-08-13 08:40 +0200
    Re: [PATCH 1/2] KVM: x86: set TMR when the interrupt is accepted Paolo Bonzini <pbonzini@redhat.com> - 2015-08-13 09:40 +0200

#1206541 — RE: [PATCH 1/2] KVM: x86: set TMR when the interrupt is accepted

Zhang, Yang Z wrote on 2015-08-04:
> Paolo Bonzini wrote on 2015-08-04:
>> 
>> 
>> On 04/08/2015 02:46, Zhang, Yang Z wrote:
>>>> It is a problem for split irqchip, where the EOI exit bitmap can
>>>> be inferred from the IOAPIC routes but the TMR cannot.  The
>>>> hardware behavior on the other hand can be implemented purely within the LAPIC.
>>> 
>>> So updating the TMR within LAPIC is the only solution to handle it?
>> 
>> It's the simplest and the one that makes most sense.  Considering
>> that TMR is a pretty obscure feature, it's unlikely that it will be
>> accelerated in the future.
> 
> You may be right. It is safe if no future hardware plans to use it.
> Let me check with our hardware team to see whether it will be used or not in future.

After checking with Jun, there is no guarantee that the guest running on another CPU will operate properly if hypervisor modify the vTMR from another CPU. So the hypervisor should not to do it.

> 
>> 
>> Paolo
> 
> 
> Best regards,
> Yang
>


Best regards,
Yang


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#1206568

On 13/08/2015 08:35, Zhang, Yang Z wrote:
>> You may be right. It is safe if no future hardware plans to use
>> it. Let me check with our hardware team to see whether it will be
>> used or not in future.
> 
> After checking with Jun, there is no guarantee that the guest running
> on another CPU will operate properly if hypervisor modify the vTMR
> from another CPU. So the hypervisor should not to do it.

I guess I can cause a vmexit on level-triggered interrupts, it's not a
big deal, but no weasel words, please.

What's going to break, and where is it documented?

Paolo
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