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[PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend

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  [PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend Grygorii Strashko <grygorii.strashko@ti.com> - 2015-08-12 19:50 +0200
    Re: [PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend Sudeep Holla <sudeep.holla@arm.com> - 2015-08-13 11:40 +0200
      Re: [PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend Grygorii Strashko <grygorii.strashko@ti.com> - 2015-08-13 12:30 +0200
        Re: [PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend Sudeep Holla <sudeep.holla@arm.com> - 2015-08-13 13:10 +0200

#1206301 — [PATCH v2 6/6] irqchip: crossbar: fix irq masking at suspend

All ARM GIC IRQs have to masked during suspend if they are not
wakeup source. Now this is not happen, since switching to
use IRQ domain hierarchy, because suspend_device_irq() only checks flags
in the last IRQ chip in hierarchy for IRQCHIP_MASK_ON_SUSPEND
bit set. And in the case of TI OMAP DRA7 the last IRQ chip is TI Crossbar
which do not have this flag set.

In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
  ARM GIC <- OMAP wakeupgen <- TI CBAR
ARM GIC - IRQCHIP_MASK_ON_SUSPEND=n
OMAP wakeupgen - IRQCHIP_MASK_ON_SUSPEND=y
TI CBAR - IRQCHIP_MASK_ON_SUSPEND=n

Hence, fix by adding IRQCHIP_MASK_ON_SUSPEND for
TI Crossbar IRQ chip.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
---
 drivers/irqchip/irq-crossbar.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 3ba58e7..f5a72cc 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -70,6 +70,7 @@ static struct irq_chip crossbar_chip = {
 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
 	.irq_set_wake		= irq_chip_set_wake_parent,
 	.irq_set_type		= irq_chip_set_type_parent,
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
 #ifdef CONFIG_SMP
 	.irq_set_affinity	= irq_chip_set_affinity_parent,
 #endif
-- 
2.5.0

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#1206655

On 12/08/15 18:46, Grygorii Strashko wrote:
> All ARM GIC IRQs have to masked during suspend if they are not
> wakeup source. Now this is not happen, since switching to
> use IRQ domain hierarchy, because suspend_device_irq() only checks flags
> in the last IRQ chip in hierarchy for IRQCHIP_MASK_ON_SUSPEND
> bit set. And in the case of TI OMAP DRA7 the last IRQ chip is TI Crossbar
> which do not have this flag set.
>
> In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
>    ARM GIC <- OMAP wakeupgen <- TI CBAR
> ARM GIC - IRQCHIP_MASK_ON_SUSPEND=n

May be this won't affect your platform or this patch but even GIC marks
IRQCHIP_MASK_ON_SUSPEND=y now since GIC doesn't provide any facility to
configure the wakeup source and keeps all the interrupt source enabled.

We have this flag enabled now as it's always safer to mask all the non
wakeup interrupts are masked at the chip level when suspending.

Also the beginning of the commit message contradicts when you also say
in the following statement IRQCHIP_MASK_ON_SUSPEND=n. So you may need to
update the log.

Regards,
Sudeep
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#1206688

On 08/13/2015 12:30 PM, Sudeep Holla wrote:
> 
> 
> On 12/08/15 18:46, Grygorii Strashko wrote:
>> All ARM GIC IRQs have to masked during suspend if they are not
>> wakeup source. Now this is not happen, since switching to
>> use IRQ domain hierarchy, because suspend_device_irq() only checks flags
>> in the last IRQ chip in hierarchy for IRQCHIP_MASK_ON_SUSPEND
>> bit set. And in the case of TI OMAP DRA7 the last IRQ chip is TI Crossbar
>> which do not have this flag set.
>>
>> In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
>>    ARM GIC <- OMAP wakeupgen <- TI CBAR
>> ARM GIC - IRQCHIP_MASK_ON_SUSPEND=n
> 
> May be this won't affect your platform or this patch but even GIC marks
> IRQCHIP_MASK_ON_SUSPEND=y now since GIC doesn't provide any facility to
> configure the wakeup source and keeps all the interrupt source enabled.

That's true for next, bur not true for 4.2-rc6 or 4.1 :(

> 
> We have this flag enabled now as it's always safer to mask all the non
> wakeup interrupts are masked at the chip level when suspending.

Indeed, but that's do not work in case of IRQ domain hierarchy and
it's do not clear how should it work?
I've tried to describe this problem in cover letter actually.

> 
> Also the beginning of the commit message contradicts when you also say
> in the following statement IRQCHIP_MASK_ON_SUSPEND=n. So you may need to
> update the log.

I'll try to reword. What I've tried to mention that IRQs masking on
suspend is default expected behavior and that how it was before
switching to IRQ domain hierarchy.

"All ARM GIC IRQs have to masked during suspend if they are not
 wakeup source - this is expected behavior and that's how it was before
 switching to IRQ domain hierarchy. ..."
ok?

-- 
regards,
-grygorii
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#1206725

On 13/08/15 11:17, Grygorii Strashko wrote:
> On 08/13/2015 12:30 PM, Sudeep Holla wrote:
>>
>>
>> On 12/08/15 18:46, Grygorii Strashko wrote:
>>> All ARM GIC IRQs have to masked during suspend if they are not
>>> wakeup source. Now this is not happen, since switching to
>>> use IRQ domain hierarchy, because suspend_device_irq() only checks flags
>>> in the last IRQ chip in hierarchy for IRQCHIP_MASK_ON_SUSPEND
>>> bit set. And in the case of TI OMAP DRA7 the last IRQ chip is TI Crossbar
>>> which do not have this flag set.
>>>
>>> In case of TI OMAP DRA7 the following IRQ hierarchy is defined:
>>>     ARM GIC <- OMAP wakeupgen <- TI CBAR
>>> ARM GIC - IRQCHIP_MASK_ON_SUSPEND=n
>>
>> May be this won't affect your platform or this patch but even GIC marks
>> IRQCHIP_MASK_ON_SUSPEND=y now since GIC doesn't provide any facility to
>> configure the wakeup source and keeps all the interrupt source enabled.
>
> That's true for next, bur not true for 4.2-rc6 or 4.1 :(
>

True, I just wanted to ensure there is no assumption.

[...]
>>
>> Also the beginning of the commit message contradicts when you also say
>> in the following statement IRQCHIP_MASK_ON_SUSPEND=n. So you may need to
>> update the log.
>
> I'll try to reword. What I've tried to mention that IRQs masking on
> suspend is default expected behavior and that how it was before
> switching to IRQ domain hierarchy.
>
> "All ARM GIC IRQs have to masked during suspend if they are not
>   wakeup source - this is expected behavior and that's how it was before
>   switching to IRQ domain hierarchy. ..."
> ok?
>

My mistake I referred the code after it was converted to use stack
domains. So I missed to understand that you were using gic_arch_extn
flags before to override GIC flags as gic_set_irqchip_flags was not
used when I removed it. Sorry for the noise, you can retain the commit
log as is.

Regards,
Sudeep
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