Groups > linux.kernel > #1200005 > unrolled thread

RE: [tip:perf/core] perf/x86: Add an MSR PMU driver

Started by	"Liang, Kan" <kan.liang@intel.com>
First post	2015-08-04 17:10 +0200
Last post	2015-08-06 19:50 +0200
Articles	13 — 3 participants

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  RE: [tip:perf/core] perf/x86: Add an MSR PMU driver "Liang, Kan" <kan.liang@intel.com> - 2015-08-04 17:10 +0200
    Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Andy Lutomirski <luto@amacapital.net> - 2015-08-04 20:10 +0200
      RE: [tip:perf/core] perf/x86: Add an MSR PMU driver "Liang, Kan" <kan.liang@intel.com> - 2015-08-04 20:20 +0200
        Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Andy Lutomirski <luto@amacapital.net> - 2015-08-04 20:20 +0200
          RE: [tip:perf/core] perf/x86: Add an MSR PMU driver "Liang, Kan" <kan.liang@intel.com> - 2015-08-04 23:00 +0200
            Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Peter Zijlstra <peterz@infradead.org> - 2015-08-06 17:30 +0200
              Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Andy Lutomirski <luto@amacapital.net> - 2015-08-06 17:40 +0200
                Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Peter Zijlstra <peterz@infradead.org> - 2015-08-06 18:00 +0200
                  Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Peter Zijlstra <peterz@infradead.org> - 2015-08-07 10:40 +0200
                    Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Andy Lutomirski <luto@amacapital.net> - 2015-08-10 04:20 +0200
                    RE: [tip:perf/core] perf/x86: Add an MSR PMU driver "Liang, Kan" <kan.liang@intel.com> - 2015-08-10 16:10 +0200
                      Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Peter Zijlstra <peterz@infradead.org> - 2015-08-10 16:30 +0200
              RE: [tip:perf/core] perf/x86: Add an MSR PMU driver "Liang, Kan" <kan.liang@intel.com> - 2015-08-06 19:50 +0200

#1200005 — RE: [tip:perf/core] perf/x86: Add an MSR PMU driver

From	"Liang, Kan" <kan.liang@intel.com>
Date	2015-08-04 17:10 +0200
Subject	RE: [tip:perf/core] perf/x86: Add an MSR PMU driver
Message-ID	<pTM0Q-5Ik-61@gated-at.bofh.it>

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#1200202

From	Andy Lutomirski <luto@amacapital.net>
Date	2015-08-04 20:10 +0200
Message-ID	<pTOP0-1jD-31@gated-at.bofh.it>
In reply to	#1200005

On Tue, Aug 4, 2015 at 8:03 AM, Liang, Kan <kan.liang@intel.com> wrote:
>
>> > +
>> > +enum perf_msr_id {
>> > +       PERF_MSR_TSC                    = 0,
>> > +       PERF_MSR_APERF                  = 1,
>> > +       PERF_MSR_MPERF                  = 2,
>> > +       PERF_MSR_PPERF                  = 3,
>> > +       PERF_MSR_SMI                    = 4,
>> > +
>> > +       PERF_MSR_EVENT_MAX,
>> > +};
>> > +
>> > +struct perf_msr {
>> > +       int     id;
>> > +       u64     msr;
>> > +};
>> > +
>> > +static struct perf_msr msr[] = {
>> > +       { PERF_MSR_TSC, 0 },
>> > +       { PERF_MSR_APERF, MSR_IA32_APERF },
>> > +       { PERF_MSR_MPERF, MSR_IA32_MPERF },
>> > +       { PERF_MSR_PPERF, MSR_PPERF },
>> > +       { PERF_MSR_SMI, MSR_SMI_COUNT }, };
>>
>> I think this could be easier to work with if it were [PERF_MSR_TSC] = {...},
>> etc.  No big deal, though, until the list gets long.  However, it might make
>> fixing the apparent issue below easier...
>>
>> > +static int msr_event_init(struct perf_event *event) {
>> > +       u64 cfg = event->attr.config;
>>
>> ...
>>
>> > +       event->hw.event_base = msr[cfg].msr;
>>
>> Shouldn't this verify that the fancy enumeration code actually believes that
>> msr[cfg] exists on this system? Otherwise we might have a very short wait
>> until the perf fuzzer oopses this thing :)
>>
>
> I think we already did the check before using msr[cfg].

Where?  All I see is:

+       if (cfg >= PERF_MSR_EVENT_MAX)
+               return -EINVAL;

--Andy
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#1200211

From	"Liang, Kan" <kan.liang@intel.com>
Date	2015-08-04 20:20 +0200
Message-ID	<pTOYG-1uV-27@gated-at.bofh.it>
In reply to	#1200202

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#1200213

From	Andy Lutomirski <luto@amacapital.net>
Date	2015-08-04 20:20 +0200
Message-ID	<pTOYG-1uV-25@gated-at.bofh.it>
In reply to	#1200211

On Tue, Aug 4, 2015 at 11:11 AM, Liang, Kan <kan.liang@intel.com> wrote:
>
>
>>
>> On Tue, Aug 4, 2015 at 8:03 AM, Liang, Kan <kan.liang@intel.com> wrote:
>> >
>> >> > +
>> >> > +enum perf_msr_id {
>> >> > +       PERF_MSR_TSC                    = 0,
>> >> > +       PERF_MSR_APERF                  = 1,
>> >> > +       PERF_MSR_MPERF                  = 2,
>> >> > +       PERF_MSR_PPERF                  = 3,
>> >> > +       PERF_MSR_SMI                    = 4,
>> >> > +
>> >> > +       PERF_MSR_EVENT_MAX,
>> >> > +};
>> >> > +
>> >> > +struct perf_msr {
>> >> > +       int     id;
>> >> > +       u64     msr;
>> >> > +};
>> >> > +
>> >> > +static struct perf_msr msr[] = {
>> >> > +       { PERF_MSR_TSC, 0 },
>> >> > +       { PERF_MSR_APERF, MSR_IA32_APERF },
>> >> > +       { PERF_MSR_MPERF, MSR_IA32_MPERF },
>> >> > +       { PERF_MSR_PPERF, MSR_PPERF },
>> >> > +       { PERF_MSR_SMI, MSR_SMI_COUNT }, };
>> >>
>> >> I think this could be easier to work with if it were [PERF_MSR_TSC] =
>> >> {...}, etc.  No big deal, though, until the list gets long.  However,
>> >> it might make fixing the apparent issue below easier...
>> >>
>> >> > +static int msr_event_init(struct perf_event *event) {
>> >> > +       u64 cfg = event->attr.config;
>> >>
>> >> ...
>> >>
>> >> > +       event->hw.event_base = msr[cfg].msr;
>> >>
>> >> Shouldn't this verify that the fancy enumeration code actually
>> >> believes that msr[cfg] exists on this system? Otherwise we might have
>> >> a very short wait until the perf fuzzer oopses this thing :)
>> >>
>> >
>> > I think we already did the check before using msr[cfg].
>>
>> Where?  All I see is:
>>
>> +       if (cfg >= PERF_MSR_EVENT_MAX)
>> +               return -EINVAL;
>
> Yes, we check cfg here. So msr[cfg] should be always available.
>

PERF_MSR_EVENT_MAX is a constant.  If I run this thing on an AMD CPU
that supports TSC, APERF, MPERF, and nothing else, and someone asks
for PPERF, then the check will succeed and we'll oops, right?

--Andy
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#1200276

From	"Liang, Kan" <kan.liang@intel.com>
Date	2015-08-04 23:00 +0200
Message-ID	<pTRtw-55z-3@gated-at.bofh.it>
In reply to	#1200213

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#1201848

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-08-06 17:30 +0200
Message-ID	<pUvhg-4zC-11@gated-at.bofh.it>
In reply to	#1200276

On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote:
> Right, it could be a problem.
> How about the patch as below?

X-MS-Has-Attach:
X-MS-TNEF-Correlator:
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64

Your outlook wrecked it, please use a less broken MUA.

How about we do the below instead? Its also virt proof by virtue of
probing if we can read the MSRs.

---
 arch/x86/kernel/cpu/perf_event_msr.c | 122 +++++++++++------------------------
 1 file changed, 39 insertions(+), 83 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_msr.c b/arch/x86/kernel/cpu/perf_event_msr.c
index af216e9223e8..e9b6a0058110 100644
--- a/arch/x86/kernel/cpu/perf_event_msr.c
+++ b/arch/x86/kernel/cpu/perf_event_msr.c
@@ -10,17 +10,21 @@ enum perf_msr_id {
 	PERF_MSR_EVENT_MAX,
 };
 
+bool test_aperfmperf(void)
+{
+	return boot_cpu_has(X86_FEATURE_APERFMPERF);
+}
+
+bool test_intel(void)
+{
+	return boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+	       boot_cpu_data.x86 == 6;
+}
+
 struct perf_msr {
-	int	id;
 	u64	msr;
-};
-
-static struct perf_msr msr[] = {
-	{ PERF_MSR_TSC, 0 },
-	{ PERF_MSR_APERF, MSR_IA32_APERF },
-	{ PERF_MSR_MPERF, MSR_IA32_MPERF },
-	{ PERF_MSR_PPERF, MSR_PPERF },
-	{ PERF_MSR_SMI, MSR_SMI_COUNT },
+	struct	perf_pmu_events_attr *attr;
+	bool	(*test)(void);
 };
 
 PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
@@ -29,8 +33,17 @@ PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
 PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
 
+static struct perf_msr msr[] = {
+	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,			},
+	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf,	},
+	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf,	},
+	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,		},
+	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,		},
+};
+
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
 	&evattr_tsc.attr.attr,
+	NULL,
 };
 
 static struct attribute_group events_attr_group = {
@@ -74,6 +87,9 @@ static int msr_event_init(struct perf_event *event)
 	    event->attr.sample_period) /* no sampling */
 		return -EINVAL;
 
+	if (!msr[cfg].attr)
+		return -EINVAL;
+
 	event->hw.idx = -1;
 	event->hw.event_base = msr[cfg].msr;
 	event->hw.config = cfg;
@@ -151,89 +167,29 @@ static struct pmu pmu_msr = {
 	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
 };
 
-static int __init intel_msr_init(int idx)
-{
-	if (boot_cpu_data.x86 != 6)
-		return 0;
-
-	switch (boot_cpu_data.x86_model) {
-	case 30: /* 45nm Nehalem    */
-	case 26: /* 45nm Nehalem-EP */
-	case 46: /* 45nm Nehalem-EX */
-
-	case 37: /* 32nm Westmere    */
-	case 44: /* 32nm Westmere-EP */
-	case 47: /* 32nm Westmere-EX */
-
-	case 42: /* 32nm SandyBridge         */
-	case 45: /* 32nm SandyBridge-E/EN/EP */
-
-	case 58: /* 22nm IvyBridge       */
-	case 62: /* 22nm IvyBridge-EP/EX */
-
-	case 60: /* 22nm Haswell Core */
-	case 63: /* 22nm Haswell Server */
-	case 69: /* 22nm Haswell ULT */
-	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
-
-	case 61: /* 14nm Broadwell Core-M */
-	case 86: /* 14nm Broadwell Xeon D */
-	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
-	case 79: /* 14nm Broadwell Server */
-		events_attrs[idx++] = &evattr_smi.attr.attr;
-		break;
-
-	case 78: /* 14nm Skylake Mobile */
-	case 94: /* 14nm Skylake Desktop */
-		events_attrs[idx++] = &evattr_pperf.attr.attr;
-		events_attrs[idx++] = &evattr_smi.attr.attr;
-		break;
-
-	case 55: /* 22nm Atom "Silvermont"                */
-	case 76: /* 14nm Atom "Airmont"                   */
-	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
-		events_attrs[idx++] = &evattr_smi.attr.attr;
-		break;
-	}
-
-	events_attrs[idx] = NULL;
-
-	return 0;
-}
-
-static int __init amd_msr_init(int idx)
-{
-	return 0;
-}
-
 static int __init msr_init(void)
 {
-	int err;
-	int idx = 1;
+	int i, j = 1;
 
-	if (boot_cpu_has(X86_FEATURE_APERFMPERF)) {
-		events_attrs[idx++] = &evattr_aperf.attr.attr;
-		events_attrs[idx++] = &evattr_mperf.attr.attr;
-		events_attrs[idx] = NULL;
+	if (!boot_cpu_has(X86_FEATURE_TSC)) {
+		pr_cont("no MSR PMU driver.\n");
+		return 0;
 	}
 
-	switch (boot_cpu_data.x86_vendor) {
-	case X86_VENDOR_INTEL:
-		err = intel_msr_init(idx);
-		break;
-
-	case X86_VENDOR_AMD:
-		err = amd_msr_init(idx);
-		break;
+	/* Probe the MSRs. */
+	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
+		u64 val;
 
-	default:
-		err = -ENOTSUPP;
+		if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
+			msr[i].attr = NULL;
 	}
 
-	if (err != 0) {
-		pr_cont("no msr PMU driver.\n");
-		return 0;
+	/* List remaining MSRs in the sysfs attrs. */
+	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
+		if (msr[i].attr)
+			events_attrs[j++] = &msr[i].attr->attr.attr;
 	}
+	events_attrs[j] = NULL;
 
 	perf_pmu_register(&pmu_msr, "msr", -1);
 
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#1201858

From	Andy Lutomirski <luto@amacapital.net>
Date	2015-08-06 17:40 +0200
Message-ID	<pUvqX-4KP-47@gated-at.bofh.it>
In reply to	#1201848

On Thu, Aug 6, 2015 at 8:21 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote:
> -       default:
> -               err = -ENOTSUPP;
> +               if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
> +                       msr[i].attr = NULL;

IIRC rdmsrl_safe literally never fails under QEMU TCG, and I'm not
entirely sure what happens under KVM if emulation kicks in.  It might
pay to keep the model check for the non-architectural stuff, or at
least check for a nonzero return value.

--Andy
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#1201872

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-08-06 18:00 +0200
Message-ID	<pUvKi-57B-15@gated-at.bofh.it>
In reply to	#1201858

On Thu, Aug 06, 2015 at 08:30:08AM -0700, Andy Lutomirski wrote:
> On Thu, Aug 6, 2015 at 8:21 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> > On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote:
> > -       default:
> > -               err = -ENOTSUPP;
> > +               if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
> > +                       msr[i].attr = NULL;
> 
> IIRC rdmsrl_safe literally never fails under QEMU TCG, and I'm not

*sigh* the borkage never stops does it :-(

> entirely sure what happens under KVM if emulation kicks in.  It might
> pay to keep the model check for the non-architectural stuff, or at
> least check for a nonzero return value.

Of course, 0 might be a valid value.. Esp. for the SMI counter.
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#1202452

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-08-07 10:40 +0200
Message-ID	<pULm2-2zq-19@gated-at.bofh.it>
In reply to	#1201872

On Thu, Aug 06, 2015 at 05:59:43PM +0200, Peter Zijlstra wrote:
> On Thu, Aug 06, 2015 at 08:30:08AM -0700, Andy Lutomirski wrote:
> > On Thu, Aug 6, 2015 at 8:21 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> > > On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote:
> > > -       default:
> > > -               err = -ENOTSUPP;
> > > +               if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
> > > +                       msr[i].attr = NULL;
> > 
> > IIRC rdmsrl_safe literally never fails under QEMU TCG, and I'm not
> 
> *sigh* the borkage never stops does it :-(
> 
> > entirely sure what happens under KVM if emulation kicks in.  It might
> > pay to keep the model check for the non-architectural stuff, or at
> > least check for a nonzero return value.
> 
> Of course, 0 might be a valid value.. Esp. for the SMI counter.

This then..

---
 arch/x86/kernel/cpu/perf_event_msr.c |  170 +++++++++++++++++------------------
 1 file changed, 85 insertions(+), 85 deletions(-)

--- a/arch/x86/kernel/cpu/perf_event_msr.c
+++ b/arch/x86/kernel/cpu/perf_event_msr.c
@@ -10,17 +10,63 @@ enum perf_msr_id {
 	PERF_MSR_EVENT_MAX,
 };
 
+bool test_aperfmperf(int idx)
+{
+	return boot_cpu_has(X86_FEATURE_APERFMPERF);
+}
+
+bool test_intel(int idx)
+{
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
+	    boot_cpu_data.x86 != 6)
+		return false;
+
+	switch (boot_cpu_data.x86_model) {
+	case 30: /* 45nm Nehalem    */
+	case 26: /* 45nm Nehalem-EP */
+	case 46: /* 45nm Nehalem-EX */
+
+	case 37: /* 32nm Westmere    */
+	case 44: /* 32nm Westmere-EP */
+	case 47: /* 32nm Westmere-EX */
+
+	case 42: /* 32nm SandyBridge         */
+	case 45: /* 32nm SandyBridge-E/EN/EP */
+
+	case 58: /* 22nm IvyBridge       */
+	case 62: /* 22nm IvyBridge-EP/EX */
+
+	case 60: /* 22nm Haswell Core */
+	case 63: /* 22nm Haswell Server */
+	case 69: /* 22nm Haswell ULT */
+	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
+
+	case 61: /* 14nm Broadwell Core-M */
+	case 86: /* 14nm Broadwell Xeon D */
+	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
+	case 79: /* 14nm Broadwell Server */
+
+	case 55: /* 22nm Atom "Silvermont"                */
+	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
+	case 76: /* 14nm Atom "Airmont"                   */
+		if (idx == PERF_MSR_SMI)
+			return true;
+		break;
+
+	case 78: /* 14nm Skylake Mobile */
+	case 94: /* 14nm Skylake Desktop */
+		if (idx == PERF_MSR_SMI || idx = PERF_MSR_PPERF)
+			return true;
+		break;
+	}
+
+	return false;
+}
+
 struct perf_msr {
-	int	id;
 	u64	msr;
-};
-
-static struct perf_msr msr[] = {
-	{ PERF_MSR_TSC, 0 },
-	{ PERF_MSR_APERF, MSR_IA32_APERF },
-	{ PERF_MSR_MPERF, MSR_IA32_MPERF },
-	{ PERF_MSR_PPERF, MSR_PPERF },
-	{ PERF_MSR_SMI, MSR_SMI_COUNT },
+	struct	perf_pmu_events_attr *attr;
+	bool	(*test)(int idx);
 };
 
 PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
@@ -29,8 +75,16 @@ PMU_EVENT_ATTR_STRING(mperf, evattr_mper
 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
 PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
 
+static struct perf_msr msr[] = {
+	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },
+	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
+	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
+	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
+	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
+};
+
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
-	&evattr_tsc.attr.attr,
+	NULL,
 };
 
 static struct attribute_group events_attr_group = {
@@ -74,6 +128,9 @@ static int msr_event_init(struct perf_ev
 	    event->attr.sample_period) /* no sampling */
 		return -EINVAL;
 
+	if (!msr[cfg].attr)
+		return -EINVAL;
+
 	event->hw.idx = -1;
 	event->hw.event_base = msr[cfg].msr;
 	event->hw.config = cfg;
@@ -151,89 +208,32 @@ static struct pmu pmu_msr = {
 	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
 };
 
-static int __init intel_msr_init(int idx)
-{
-	if (boot_cpu_data.x86 != 6)
-		return 0;
-
-	switch (boot_cpu_data.x86_model) {
-	case 30: /* 45nm Nehalem    */
-	case 26: /* 45nm Nehalem-EP */
-	case 46: /* 45nm Nehalem-EX */
-
-	case 37: /* 32nm Westmere    */
-	case 44: /* 32nm Westmere-EP */
-	case 47: /* 32nm Westmere-EX */
-
-	case 42: /* 32nm SandyBridge         */
-	case 45: /* 32nm SandyBridge-E/EN/EP */
-
-	case 58: /* 22nm IvyBridge       */
-	case 62: /* 22nm IvyBridge-EP/EX */
-
-	case 60: /* 22nm Haswell Core */
-	case 63: /* 22nm Haswell Server */
-	case 69: /* 22nm Haswell ULT */
-	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
-
-	case 61: /* 14nm Broadwell Core-M */
-	case 86: /* 14nm Broadwell Xeon D */
-	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
-	case 79: /* 14nm Broadwell Server */
-		events_attrs[idx++] = &evattr_smi.attr.attr;
-		break;
-
-	case 78: /* 14nm Skylake Mobile */
-	case 94: /* 14nm Skylake Desktop */
-		events_attrs[idx++] = &evattr_pperf.attr.attr;
-		events_attrs[idx++] = &evattr_smi.attr.attr;
-		break;
-
-	case 55: /* 22nm Atom "Silvermont"                */
-	case 76: /* 14nm Atom "Airmont"                   */
-	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
-		events_attrs[idx++] = &evattr_smi.attr.attr;
-		break;
-	}
-
-	events_attrs[idx] = NULL;
-
-	return 0;
-}
-
-static int __init amd_msr_init(int idx)
-{
-	return 0;
-}
-
 static int __init msr_init(void)
 {
-	int err;
-	int idx = 1;
+	int i, j = 0;
 
-	if (boot_cpu_has(X86_FEATURE_APERFMPERF)) {
-		events_attrs[idx++] = &evattr_aperf.attr.attr;
-		events_attrs[idx++] = &evattr_mperf.attr.attr;
-		events_attrs[idx] = NULL;
+	if (!boot_cpu_has(X86_FEATURE_TSC)) {
+		pr_cont("no MSR PMU driver.\n");
+		return 0;
 	}
 
-	switch (boot_cpu_data.x86_vendor) {
-	case X86_VENDOR_INTEL:
-		err = intel_msr_init(idx);
-		break;
-
-	case X86_VENDOR_AMD:
-		err = amd_msr_init(idx);
-		break;
-
-	default:
-		err = -ENOTSUPP;
+	/* Probe the MSRs. */
+	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
+		u64 val;
+
+		/*
+		 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
+		 */
+		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
+			msr[i].attr = NULL;
 	}
 
-	if (err != 0) {
-		pr_cont("no msr PMU driver.\n");
-		return 0;
+	/* List remaining MSRs in the sysfs attrs. */
+	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
+		if (msr[i].attr)
+			events_attrs[j++] = &msr[i].attr->attr.attr;
 	}
+	events_attrs[j] = NULL;
 
 	perf_pmu_register(&pmu_msr, "msr", -1);
 
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#1203748

From	Andy Lutomirski <luto@amacapital.net>
Date	2015-08-10 04:20 +0200
Message-ID	<pVKQV-881-3@gated-at.bofh.it>
In reply to	#1202452

On Fri, Aug 7, 2015 at 1:34 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Thu, Aug 06, 2015 at 05:59:43PM +0200, Peter Zijlstra wrote:
>> On Thu, Aug 06, 2015 at 08:30:08AM -0700, Andy Lutomirski wrote:
>> > On Thu, Aug 6, 2015 at 8:21 AM, Peter Zijlstra <peterz@infradead.org> wrote:
>> > > On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote:
>> > > -       default:
>> > > -               err = -ENOTSUPP;
>> > > +               if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
>> > > +                       msr[i].attr = NULL;
>> >
>> > IIRC rdmsrl_safe literally never fails under QEMU TCG, and I'm not
>>
>> *sigh* the borkage never stops does it :-(
>>
>> > entirely sure what happens under KVM if emulation kicks in.  It might
>> > pay to keep the model check for the non-architectural stuff, or at
>> > least check for a nonzero return value.
>>
>> Of course, 0 might be a valid value.. Esp. for the SMI counter.
>
> This then..
>

LGTM on brief inspection.

--Andy
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#1204309

From	"Liang, Kan" <kan.liang@intel.com>
Date	2015-08-10 16:10 +0200
Message-ID	<pVVW2-7v-27@gated-at.bofh.it>
In reply to	#1202452


> On Thu, Aug 06, 2015 at 05:59:43PM +0200, Peter Zijlstra wrote:
> > On Thu, Aug 06, 2015 at 08:30:08AM -0700, Andy Lutomirski wrote:
> > > On Thu, Aug 6, 2015 at 8:21 AM, Peter Zijlstra <peterz@infradead.org>
> wrote:
> > > > On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote:
> > > > -       default:
> > > > -               err = -ENOTSUPP;
> > > > +               if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
> > > > +                       msr[i].attr = NULL;
> > >
> > > IIRC rdmsrl_safe literally never fails under QEMU TCG, and I'm not
> >
> > *sigh* the borkage never stops does it :-(
> >
> > > entirely sure what happens under KVM if emulation kicks in.  It
> > > might pay to keep the model check for the non-architectural stuff,
> > > or at least check for a nonzero return value.
> >
> > Of course, 0 might be a valid value.. Esp. for the SMI counter.
> 
> This then..
> 
> ---
>  arch/x86/kernel/cpu/perf_event_msr.c |  170 +++++++++++++++++-------
> -----------
>  1 file changed, 85 insertions(+), 85 deletions(-)
> 
> --- a/arch/x86/kernel/cpu/perf_event_msr.c
> +++ b/arch/x86/kernel/cpu/perf_event_msr.c
> @@ -10,17 +10,63 @@ enum perf_msr_id {
>  	PERF_MSR_EVENT_MAX,
>  };
> 
> +bool test_aperfmperf(int idx)
> +{
> +	return boot_cpu_has(X86_FEATURE_APERFMPERF);
> +}
> +
> +bool test_intel(int idx)
> +{
> +	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> +	    boot_cpu_data.x86 != 6)
> +		return false;
> +
> +	switch (boot_cpu_data.x86_model) {
> +	case 30: /* 45nm Nehalem    */
> +	case 26: /* 45nm Nehalem-EP */
> +	case 46: /* 45nm Nehalem-EX */
> +
> +	case 37: /* 32nm Westmere    */
> +	case 44: /* 32nm Westmere-EP */
> +	case 47: /* 32nm Westmere-EX */
> +
> +	case 42: /* 32nm SandyBridge         */
> +	case 45: /* 32nm SandyBridge-E/EN/EP */
> +
> +	case 58: /* 22nm IvyBridge       */
> +	case 62: /* 22nm IvyBridge-EP/EX */
> +
> +	case 60: /* 22nm Haswell Core */
> +	case 63: /* 22nm Haswell Server */
> +	case 69: /* 22nm Haswell ULT */
> +	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
> +
> +	case 61: /* 14nm Broadwell Core-M */
> +	case 86: /* 14nm Broadwell Xeon D */
> +	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
> +	case 79: /* 14nm Broadwell Server */
> +
> +	case 55: /* 22nm Atom "Silvermont"                */
> +	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
> +	case 76: /* 14nm Atom "Airmont"                   */
> +		if (idx == PERF_MSR_SMI)
> +			return true;
> +		break;
> +
> +	case 78: /* 14nm Skylake Mobile */
> +	case 94: /* 14nm Skylake Desktop */
> +		if (idx == PERF_MSR_SMI || idx = PERF_MSR_PPERF)

Here is a typo.  The rest is OK for me.
I did some simple test on HSX.

Tested-by: Kan Liang <kan.liang@intel.com>

> +			return true;
> +		break;
> +	}
> +
> +	return false;
> +}
> +
>  struct perf_msr {
> -	int	id;
>  	u64	msr;
> -};
> -
> -static struct perf_msr msr[] = {
> -	{ PERF_MSR_TSC, 0 },
> -	{ PERF_MSR_APERF, MSR_IA32_APERF },
> -	{ PERF_MSR_MPERF, MSR_IA32_MPERF },
> -	{ PERF_MSR_PPERF, MSR_PPERF },
> -	{ PERF_MSR_SMI, MSR_SMI_COUNT },
> +	struct	perf_pmu_events_attr *attr;
> +	bool	(*test)(int idx);
>  };
> 
>  PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
> @@ -29,8 +75,16 @@ PMU_EVENT_ATTR_STRING(mperf, evattr_mper
> PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
>  PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
> 
> +static struct perf_msr msr[] = {
> +	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,
> 	NULL,		 },
> +	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,
> 	test_aperfmperf, },
> +	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,
> 	test_aperfmperf, },
> +	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,
> 	test_intel,	 },
> +	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,
> 	test_intel,	 },
> +};
> +
>  static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
> -	&evattr_tsc.attr.attr,
> +	NULL,
>  };
> 
>  static struct attribute_group events_attr_group = { @@ -74,6 +128,9 @@
> static int msr_event_init(struct perf_ev
>  	    event->attr.sample_period) /* no sampling */
>  		return -EINVAL;
> 
> +	if (!msr[cfg].attr)
> +		return -EINVAL;
> +
>  	event->hw.idx = -1;
>  	event->hw.event_base = msr[cfg].msr;
>  	event->hw.config = cfg;
> @@ -151,89 +208,32 @@ static struct pmu pmu_msr = {
>  	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
>  };
> 
> -static int __init intel_msr_init(int idx) -{
> -	if (boot_cpu_data.x86 != 6)
> -		return 0;
> -
> -	switch (boot_cpu_data.x86_model) {
> -	case 30: /* 45nm Nehalem    */
> -	case 26: /* 45nm Nehalem-EP */
> -	case 46: /* 45nm Nehalem-EX */
> -
> -	case 37: /* 32nm Westmere    */
> -	case 44: /* 32nm Westmere-EP */
> -	case 47: /* 32nm Westmere-EX */
> -
> -	case 42: /* 32nm SandyBridge         */
> -	case 45: /* 32nm SandyBridge-E/EN/EP */
> -
> -	case 58: /* 22nm IvyBridge       */
> -	case 62: /* 22nm IvyBridge-EP/EX */
> -
> -	case 60: /* 22nm Haswell Core */
> -	case 63: /* 22nm Haswell Server */
> -	case 69: /* 22nm Haswell ULT */
> -	case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
> -
> -	case 61: /* 14nm Broadwell Core-M */
> -	case 86: /* 14nm Broadwell Xeon D */
> -	case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
> -	case 79: /* 14nm Broadwell Server */
> -		events_attrs[idx++] = &evattr_smi.attr.attr;
> -		break;
> -
> -	case 78: /* 14nm Skylake Mobile */
> -	case 94: /* 14nm Skylake Desktop */
> -		events_attrs[idx++] = &evattr_pperf.attr.attr;
> -		events_attrs[idx++] = &evattr_smi.attr.attr;
> -		break;
> -
> -	case 55: /* 22nm Atom "Silvermont"                */
> -	case 76: /* 14nm Atom "Airmont"                   */
> -	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
> -		events_attrs[idx++] = &evattr_smi.attr.attr;
> -		break;
> -	}
> -
> -	events_attrs[idx] = NULL;
> -
> -	return 0;
> -}
> -
> -static int __init amd_msr_init(int idx) -{
> -	return 0;
> -}
> -
>  static int __init msr_init(void)
>  {
> -	int err;
> -	int idx = 1;
> +	int i, j = 0;
> 
> -	if (boot_cpu_has(X86_FEATURE_APERFMPERF)) {
> -		events_attrs[idx++] = &evattr_aperf.attr.attr;
> -		events_attrs[idx++] = &evattr_mperf.attr.attr;
> -		events_attrs[idx] = NULL;
> +	if (!boot_cpu_has(X86_FEATURE_TSC)) {
> +		pr_cont("no MSR PMU driver.\n");
> +		return 0;
>  	}
> 
> -	switch (boot_cpu_data.x86_vendor) {
> -	case X86_VENDOR_INTEL:
> -		err = intel_msr_init(idx);
> -		break;
> -
> -	case X86_VENDOR_AMD:
> -		err = amd_msr_init(idx);
> -		break;
> -
> -	default:
> -		err = -ENOTSUPP;
> +	/* Probe the MSRs. */
> +	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
> +		u64 val;
> +
> +		/*
> +		 * Virt sucks arse; you cannot tell if a R/O MSR is present :/
> +		 */
> +		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
> +			msr[i].attr = NULL;
>  	}
> 
> -	if (err != 0) {
> -		pr_cont("no msr PMU driver.\n");
> -		return 0;
> +	/* List remaining MSRs in the sysfs attrs. */
> +	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
> +		if (msr[i].attr)
> +			events_attrs[j++] = &msr[i].attr->attr.attr;
>  	}
> +	events_attrs[j] = NULL;
> 
>  	perf_pmu_register(&pmu_msr, "msr", -1);
> 
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#1204326

From	Peter Zijlstra <peterz@infradead.org>
Date	2015-08-10 16:30 +0200
Message-ID	<pVWfo-uE-23@gated-at.bofh.it>
In reply to	#1204309

On Mon, Aug 10, 2015 at 02:02:17PM +0000, Liang, Kan wrote:
> > +	case 94: /* 14nm Skylake Desktop */
> > +		if (idx == PERF_MSR_SMI || idx = PERF_MSR_PPERF)
> 
> Here is a typo.  The rest is OK for me.
> I did some simple test on HSX.

Yep, fixed that already.

> Tested-by: Kan Liang <kan.liang@intel.com>

Thanks!
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#1201938

From	"Liang, Kan" <kan.liang@intel.com>
Date	2015-08-06 19:50 +0200
Message-ID	<pUxsJ-7Gk-7@gated-at.bofh.it>
In reply to	#1201848


> +	/* Probe the MSRs. */
> +	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
> +		u64 val;
> 
> -	default:
> -		err = -ENOTSUPP;
> +		if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val))
> +			msr[i].attr = NULL;
>  	}
> 
> -	if (err != 0) {
> -		pr_cont("no msr PMU driver.\n");
> -		return 0;
> +	/* List remaining MSRs in the sysfs attrs. */
> +	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {

i should start from PERF_MSR_TSC + 1. The tsc has already been
inserted into events_attrs by default.

> +		if (msr[i].attr)
> +			events_attrs[j++] = &msr[i].attr->attr.attr;
>  	}
> +	events_attrs[j] = NULL;
> 
>  	perf_pmu_register(&pmu_msr, "msr", -1);
> 
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csiph-web

RE: [tip:perf/core] perf/x86: Add an MSR PMU driver

Contents

#1200005 — RE: [tip:perf/core] perf/x86: Add an MSR PMU driver

#1200202

#1200211

#1200213

#1200276

#1201848

#1201858

#1201872

#1202452

#1203748

#1204309

#1204326

#1201938