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[PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups

Started byPaul Burton <paul.burton@imgtec.com>
First post2015-08-06 00:50 +0200
Last post2015-08-06 16:00 +0200
Articles 7 — 2 participants

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  [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups Paul Burton <paul.burton@imgtec.com> - 2015-08-06 00:50 +0200
    [PATCH 5/6] MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2 Paul Burton <paul.burton@imgtec.com> - 2015-08-06 00:50 +0200
    [PATCH 3/6] MIPS: CPS: don't include MT code in non-MT kernels Paul Burton <paul.burton@imgtec.com> - 2015-08-06 00:50 +0200
    [PATCH 2/6] MIPS: CPS: stop dangling delay slot from has_mt Paul Burton <paul.burton@imgtec.com> - 2015-08-06 00:50 +0200
    [PATCH 4/6] MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT Paul Burton <paul.burton@imgtec.com> - 2015-08-06 00:50 +0200
    RE: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups Govindraj Raja <Govindraj.Raja@imgtec.com> - 2015-08-06 13:10 +0200
      RE: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups Govindraj Raja <Govindraj.Raja@imgtec.com> - 2015-08-06 16:00 +0200

#1201318 — [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups

FromPaul Burton <paul.burton@imgtec.com>
Date2015-08-06 00:50 +0200
Subject[PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
Message-ID<pUfFw-6J8-3@gated-at.bofh.it>
This series fixes a few issues with the MIPS Coherent Processing System
SMP implementation, provides some extra capabilities with regards to
debug and does a little spring cleaning. A couple of the issues fixed
were introduced in v4.1-rc1 and (spuriously) marked for stable backports
as far as v3.16, so the fixes in this series are marked likewise.

Applies atop v4.2-rc5.

Paul Burton (6):
  MIPS: CPS: use 32b accesses to GCRs
  MIPS: CPS: stop dangling delay slot from has_mt
  MIPS: CPS: don't include MT code in non-MT kernels
  MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
  MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
  MIPS: CPS: drop .set mips64r2 directives

 arch/mips/Kconfig          |  2 +-
 arch/mips/kernel/cps-vec.S | 18 +++++++++---------
 2 files changed, 10 insertions(+), 10 deletions(-)

-- 
2.5.0

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#1201319 — [PATCH 5/6] MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2

FromPaul Burton <paul.burton@imgtec.com>
Date2015-08-06 00:50 +0200
Subject[PATCH 5/6] MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
Message-ID<pUfFw-6J8-15@gated-at.bofh.it>
In reply to#1201318
The MT ASE cannot be used with CPUs that implement older releases of the
MIPS architecture than release 2, and is replaced in release 6. Encode
these constraints in Kconfig to ensure that MT code is only built as
part of kernels targeting an appropriate revision of the architecture.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.16+
---

 arch/mips/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cee5f93..ef248cf 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2114,7 +2114,7 @@ config CPU_R4K_CACHE_TLB
 
 config MIPS_MT_SMP
 	bool "MIPS MT SMP support (1 TC on each available VPE)"
-	depends on SYS_SUPPORTS_MULTITHREADING
+	depends on SYS_SUPPORTS_MULTITHREADING && CPU_MIPSR2
 	select CPU_MIPSR2_IRQ_VI
 	select CPU_MIPSR2_IRQ_EI
 	select SYNC_R4K
-- 
2.5.0

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#1201322 — [PATCH 3/6] MIPS: CPS: don't include MT code in non-MT kernels

FromPaul Burton <paul.burton@imgtec.com>
Date2015-08-06 00:50 +0200
Subject[PATCH 3/6] MIPS: CPS: don't include MT code in non-MT kernels
Message-ID<pUfFx-6J8-19@gated-at.bofh.it>
In reply to#1201318
The MT-specific code in mips_cps_boot_vpes can safely be omitted from
kernels which don't support MT, with the default VPE==0 case being used
as it would be after the has_mt (Config3.MT) check failed at runtime.
Discarding the code entirely will save us a few bytes & allow cleaner
handling of MT ASE instructions by later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.16+
---

 arch/mips/kernel/cps-vec.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index fa159aa..57642f5 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -311,6 +311,7 @@ LEAF(mips_cps_boot_vpes)
 
 	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
 	li	t9, 0
+#ifdef CONFIG_MIPS_MT
 	has_mt	ta2, 1f
 
 	/* Find the number of VPEs present in the core */
@@ -330,6 +331,7 @@ LEAF(mips_cps_boot_vpes)
 	/* Retrieve the VPE ID from EBase.CPUNum */
 	mfc0	t9, $15, 1
 	and	t9, t9, t1
+#endif
 
 1:	/* Calculate a pointer to this VPEs struct vpe_boot_config */
 	li	t1, VPEBOOTCFG_SIZE
-- 
2.5.0

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#1201323 — [PATCH 2/6] MIPS: CPS: stop dangling delay slot from has_mt

FromPaul Burton <paul.burton@imgtec.com>
Date2015-08-06 00:50 +0200
Subject[PATCH 2/6] MIPS: CPS: stop dangling delay slot from has_mt
Message-ID<pUfFw-6J8-17@gated-at.bofh.it>
In reply to#1201318
The has_mt macro ended with a branch, leaving its callers with a delay
slot that would be executed if Config3.MT is not set. However it would
not be executed if Config3 (or earlier Config registers) don't exist
which makes it somewhat inconsistent at best. Fill the delay slot in the
macro & fix the mips_cps_boot_vpes caller appropriately.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.16+
---

 arch/mips/kernel/cps-vec.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 9f71c06..fa159aa 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -39,6 +39,7 @@
 	 mfc0	\dest, CP0_CONFIG, 3
 	andi	\dest, \dest, MIPS_CONF3_MT
 	beqz	\dest, \nomt
+	 nop
 	.endm
 
 .section .text.cps-vec
@@ -226,7 +227,6 @@ LEAF(mips_cps_core_init)
 #ifdef CONFIG_MIPS_MT
 	/* Check that the core implements the MT ASE */
 	has_mt	t0, 3f
-	 nop
 
 	.set	push
 	.set	mips64r2
@@ -310,8 +310,8 @@ LEAF(mips_cps_boot_vpes)
 	PTR_ADDU t0, t0, t1
 
 	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
+	li	t9, 0
 	has_mt	ta2, 1f
-	 li	t9, 0
 
 	/* Find the number of VPEs present in the core */
 	mfc0	t1, CP0_MVPCONF0
-- 
2.5.0

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#1201324 — [PATCH 4/6] MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT

FromPaul Burton <paul.burton@imgtec.com>
Date2015-08-06 00:50 +0200
Subject[PATCH 4/6] MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
Message-ID<pUfFx-6J8-21@gated-at.bofh.it>
In reply to#1201318
The CONFIG_MIPS_MT symbol can be selected by CONFIG_MIPS_VPE_LOADER in
addition to CONFIG_MIPS_MT_SMP. We only want MT code in the CPS SMP boot
vector if we're using MT for SMP. Thus switch the config symbol we ifdef
against to CONFIG_MIPS_MT_SMP.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.16+
---

 arch/mips/kernel/cps-vec.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 57642f5..209ded1 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -224,7 +224,7 @@ LEAF(excep_ejtag)
 	END(excep_ejtag)
 
 LEAF(mips_cps_core_init)
-#ifdef CONFIG_MIPS_MT
+#ifdef CONFIG_MIPS_MT_SMP
 	/* Check that the core implements the MT ASE */
 	has_mt	t0, 3f
 
@@ -311,7 +311,7 @@ LEAF(mips_cps_boot_vpes)
 
 	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
 	li	t9, 0
-#ifdef CONFIG_MIPS_MT
+#ifdef CONFIG_MIPS_MT_SMP
 	has_mt	ta2, 1f
 
 	/* Find the number of VPEs present in the core */
@@ -339,7 +339,7 @@ LEAF(mips_cps_boot_vpes)
 	PTR_L	ta3, COREBOOTCFG_VPECONFIG(t0)
 	PTR_ADDU v0, v0, ta3
 
-#ifdef CONFIG_MIPS_MT
+#ifdef CONFIG_MIPS_MT_SMP
 
 	/* If the core doesn't support MT then return */
 	bnez	ta2, 1f
@@ -453,7 +453,7 @@ LEAF(mips_cps_boot_vpes)
 
 2:	.set	pop
 
-#endif /* CONFIG_MIPS_MT */
+#endif /* CONFIG_MIPS_MT_SMP */
 
 	/* Return */
 	jr	ra
-- 
2.5.0

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#1201647

FromGovindraj Raja <Govindraj.Raja@imgtec.com>
Date2015-08-06 13:10 +0200
Message-ID<pUrdF-77S-29@gated-at.bofh.it>
In reply to#1201318
Hi Paul / Rafl,

> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-
> mips.org] On Behalf Of Paul Burton
> Sent: 05 August 2015 11:43 PM
> To: linux-mips@linux-mips.org
> Cc: Paul Burton; linux-kernel@vger.kernel.org; James Hogan; Markos Chandras;
> Ralf Baechle
> Subject: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
> 
> This series fixes a few issues with the MIPS Coherent Processing System SMP
> implementation, provides some extra capabilities with regards to debug and does
> a little spring cleaning. A couple of the issues fixed were introduced in v4.1-rc1
> and (spuriously) marked for stable backports as far as v3.16, so the fixes in this
> series are marked likewise.
> 
> Applies atop v4.2-rc5.
> 
> Paul Burton (6):
>   MIPS: CPS: use 32b accesses to GCRs
>   MIPS: CPS: stop dangling delay slot from has_mt
>   MIPS: CPS: don't include MT code in non-MT kernels
>   MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
>   MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
>   MIPS: CPS: drop .set mips64r2 directives
> 
>  arch/mips/Kconfig          |  2 +-
>  arch/mips/kernel/cps-vec.S | 18 +++++++++---------
>  2 files changed, 10 insertions(+), 10 deletions(-)

I just boot tested on Pistachio Platform (MIPS interAptiv (multi) (32)).
Without this patch series boot is broken for pistachio platform for 4.2-rc5.

--
Thanks,
Govindraj.R
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#1201759

FromGovindraj Raja <Govindraj.Raja@imgtec.com>
Date2015-08-06 16:00 +0200
Message-ID<pUtSa-2in-21@gated-at.bofh.it>
In reply to#1201647
> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-
> mips.org] On Behalf Of Govindraj Raja
> Sent: 06 August 2015 12:05 PM
> To: Paul Burton; linux-mips@linux-mips.org; Ralf Baechle (ralf@linux-mips.org)
> Cc: linux-kernel@vger.kernel.org; James Hogan; Markos Chandras; Ralf Baechle
> Subject: RE: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
> 
> Hi Paul / Rafl,
> 
> > -----Original Message-----
> > From: linux-mips-bounce@linux-mips.org
> > [mailto:linux-mips-bounce@linux- mips.org] On Behalf Of Paul Burton
> > Sent: 05 August 2015 11:43 PM
> > To: linux-mips@linux-mips.org
> > Cc: Paul Burton; linux-kernel@vger.kernel.org; James Hogan; Markos
> > Chandras; Ralf Baechle
> > Subject: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
> >
> > This series fixes a few issues with the MIPS Coherent Processing
> > System SMP implementation, provides some extra capabilities with
> > regards to debug and does a little spring cleaning. A couple of the
> > issues fixed were introduced in v4.1-rc1 and (spuriously) marked for
> > stable backports as far as v3.16, so the fixes in this series are marked likewise.
> >
> > Applies atop v4.2-rc5.
> >
> > Paul Burton (6):
> >   MIPS: CPS: use 32b accesses to GCRs
> >   MIPS: CPS: stop dangling delay slot from has_mt
> >   MIPS: CPS: don't include MT code in non-MT kernels
> >   MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
> >   MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
> >   MIPS: CPS: drop .set mips64r2 directives
> >
> >  arch/mips/Kconfig          |  2 +-
> >  arch/mips/kernel/cps-vec.S | 18 +++++++++---------
> >  2 files changed, 10 insertions(+), 10 deletions(-)

Tested-by: Govindraj Raja <govindraj.raja@imgtec.com>
[For Pistachio Platform]

--
Thanks,
Govindraj.R
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