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| Started by | Vikas Shivappa <vikas.shivappa@intel.com> |
|---|---|
| First post | 2015-08-04 23:00 +0200 |
| Last post | 2015-08-04 23:00 +0200 |
| Articles | 1 — 1 participant |
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Re: [PATCH 3/9] x86/intel_rdt: Cache Allocation documentation and cgroup usage guide Vikas Shivappa <vikas.shivappa@intel.com> - 2015-08-04 23:00 +0200
| From | Vikas Shivappa <vikas.shivappa@intel.com> |
|---|---|
| Date | 2015-08-04 23:00 +0200 |
| Subject | Re: [PATCH 3/9] x86/intel_rdt: Cache Allocation documentation and cgroup usage guide |
| Message-ID | <pTRtw-55z-9@gated-at.bofh.it> |
On Tue, 28 Jul 2015, Peter Zijlstra wrote: > On Wed, Jul 01, 2015 at 03:21:04PM -0700, Vikas Shivappa wrote: > > Please edit this document to have consistent spacing. Its really hard to > read this. Every time I spot a misplaced space my brain stumbles and I > need to restart. Will fix all the spacing and other indentions issues mentioned. Thanks for pointing them all out. Although the other documents I see dont have a consistent format completely which is what confused me, this format would be better. >> + >> +The following considerations are done for the PQR MSR write so that it >> +has minimal impact on scheduling hot path: >> +- This path doesnt exist on any non-intel platforms. > > !x86 I think you mean, its entirely possible to have the code present > on AMD systems for instance. > >> +- On Intel platforms, this would not exist by default unless CGROUP_RDT >> +is enabled. > > You can enable this just fine on AMD machines. The cache alloc code is under CPU_SUP_INTEL .. Thanks, Vikas -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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