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Groups > linux.kernel > #1195003 > unrolled thread
| Started by | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| First post | 2015-07-29 12:10 +0200 |
| Last post | 2015-08-12 21:30 +0200 |
| Articles | 20 on this page of 40 — 6 participants |
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[PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:10 +0200
[PATCH v4 10/10] irqchip / gicv2m: Introducing gicv2m_acpi_init() Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 10/10] irqchip / gicv2m: Introducing gicv2m_acpi_init() Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 16:30 +0200
[PATCH v4 03/10] irqchip / GIC / ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
[PATCH v4 09/10] PCI: ACPI: Bind GIC MSI frame to PCI host bridge Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 09/10] PCI: ACPI: Bind GIC MSI frame to PCI host bridge Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 16:10 +0200
Re: [PATCH v4 09/10] PCI: ACPI: Bind GIC MSI frame to PCI host bridge Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-07 10:50 +0200
Re: [PATCH v4 09/10] PCI: ACPI: Bind GIC MSI frame to PCI host bridge Tomasz Nowicki <tomasz.nowicki@linaro.org> - 2015-08-07 12:10 +0200
Re: [PATCH v4 09/10] PCI: ACPI: Bind GIC MSI frame to PCI host bridge Mark Brown <broonie@kernel.org> - 2015-08-07 12:50 +0200
Re: [PATCH v4 09/10] PCI: ACPI: Bind GIC MSI frame to PCI host bridge Marc Zyngier <marc.zyngier@arm.com> - 2015-08-07 14:10 +0200
[PATCH v4 08/10] ACPI: GIC: Add ACPI helper functions to query irq-domain tokens for for GIC MSI and ITS Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 08/10] ACPI: GIC: Add ACPI helper functions to query irq-domain tokens for for GIC MSI and ITS Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 16:10 +0200
[PATCH v4 01/10] irqchip / GIC: Add GIC version support in ACPI MADT Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 01/10] irqchip / GIC: Add GIC version support in ACPI MADT Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 14:10 +0200
Re: [PATCH v4 01/10] irqchip / GIC: Add GIC version support in ACPI MADT Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-05 14:50 +0200
Re: [PATCH v4 01/10] irqchip / GIC: Add GIC version support in ACPI MADT Marc Zyngier <marc.zyngier@arm.com> - 2015-08-05 15:00 +0200
Re: [PATCH v4 01/10] irqchip / GIC: Add GIC version support in ACPI MADT Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-05 15:20 +0200
[PATCH v4 02/10] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 02/10] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 14:30 +0200
Re: [PATCH v4 02/10] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-05 15:30 +0200
Re: [PATCH v4 02/10] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller Marc Zyngier <marc.zyngier@arm.com> - 2015-08-06 18:30 +0200
[PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 15:20 +0200
Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-05 16:10 +0200
Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization Marc Zyngier <marc.zyngier@arm.com> - 2015-08-06 18:50 +0200
Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-11 09:30 +0200
[PATCH v4 05/10] irqchip / GICv3: remove the useless comparision of device node in xlate Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
[PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures Marc Zyngier <marc.zyngier@arm.com> - 2015-08-04 15:40 +0200
Re: [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures Hanjun Guo <hanjun.guo@linaro.org> - 2015-08-05 16:20 +0200
Re: [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures Marc Zyngier <marc.zyngier@arm.com> - 2015-08-06 18:50 +0200
[PATCH v4 04/10] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-29 12:20 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Timur Tabi <timur@codeaurora.org> - 2015-08-12 00:10 +0200
Re: [Linaro-acpi] [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support G Gregory <graeme.gregory@linaro.org> - 2015-08-12 00:30 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Marc Zyngier <marc.zyngier@arm.com> - 2015-08-12 00:30 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Timur Tabi <timur@codeaurora.org> - 2015-08-12 00:40 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Marc Zyngier <marc.zyngier@arm.com> - 2015-08-12 00:50 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Timur Tabi <timur@codeaurora.org> - 2015-08-12 01:40 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Marc Zyngier <marc.zyngier@arm.com> - 2015-08-12 09:30 +0200
Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support Timur Tabi <timur@codeaurora.org> - 2015-08-12 21:30 +0200
Page 2 of 2 — ← Prev page 1 [2]
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-06 18:30 +0200 |
| Subject | Re: [PATCH v4 02/10] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller |
| Message-ID | <pUwdk-5WC-15@gated-at.bofh.it> |
| In reply to | #1200732 |
On 05/08/15 14:24, Hanjun Guo wrote:
> Hi Marc,
>
> On 08/04/2015 08:27 PM, Marc Zyngier wrote:
>> On 29/07/15 11:08, Hanjun Guo wrote:
>>> This self-probe infrastructure works in the similar way as OF,
>>> but there is some different in the mechanism:
>>>
>>> For DT, the init fn will be called once it finds compatible strings
>>> in DT, but for ACPI, we init irqchips by static tables, and in
>>> static ACPI tables, there are no compatible strings to indicate
>>> irqchips, but thanks to the GIC version presented in ACPI table,
>>> we can call the corresponding GIC drivers matching the GIC version
>>> with this framework.
>>>
>>> This mechanism can also be used for clock declare and may also works
>>> on x86 for some table parsing too.
>>>
>>> This patch is based on Tomasz Nowicki <tomasz.nowicki@linaro.org>'s
>>> work.
>>>
>>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>>> ---
>>> drivers/irqchip/irq-gic-acpi.c | 33 +++++++++++++++++++++++++++++++++
>>> include/asm-generic/vmlinux.lds.h | 13 +++++++++++++
>>> include/linux/acpi.h | 16 ++++++++++++++++
>>> include/linux/irqchip.h | 13 +++++++++++++
>>> include/linux/mod_devicetable.h | 8 ++++++++
>>> 5 files changed, 83 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c
>>> index 6537b43..011468d 100644
>>> --- a/drivers/irqchip/irq-gic-acpi.c
>>> +++ b/drivers/irqchip/irq-gic-acpi.c
>>> @@ -107,3 +107,36 @@ static int __init acpi_gic_version_init(void)
>>>
>>> return 0;
>>> }
>>> +
>>> +/*
>>> + * This special acpi_table_id is the sentinel at the end of the
>>> + * acpi_table_id[] array of all irqchips. It is automatically placed at
>>> + * the end of the array by the linker, thanks to being part of a
>>> + * special section.
>>> + */
>>> +static const struct acpi_table_id
>>> +irqchip_acpi_match_end __used __section(__irqchip_acpi_table_end);
>>
>> What is this thing for? Nobody refers to it (I know
>> drivers/irqchip/irqchip.c has a similar thing, but that's not enough a
>> reason...).
>
> If I'm not mistaken, this is for proper section termination, please
> see below:
>
> /* scan the irqchip table to match the GIC version and its driver */
> for (id = __irqchip_acpi_table; id->id[0]; id++) {
> ...
> }
>
> Then irqchip_acpi_match_end will be the end of the table section,
> which will terminate the scanning.
Yeah, I got that bit, but I didn't realized this was getting pulled into
the section. It's probably fine then.
>>
>>> +
>>> +extern struct acpi_table_id __irqchip_acpi_table[];
>>> +
>>> +void __init acpi_irqchip_init(void)
>>> +{
>>> + struct acpi_table_id *id;
>>> +
>>> + if (acpi_disabled)
>>> + return;
>>> +
>>> + if (acpi_gic_version_init())
>>> + return;
>>
>> This is the only place where we need the version, right? So just get
>> acpi_gic_version_init to return the version number, and loose the global
>> variable.
>
> The global variable is still needed because we need to get the GIC
> version when scanning the MADT tables, we can't return the table value
> directly in acpi_table_parse_madt() at now.
>
>>
>>> +
>>> + /* scan the irqchip table to match the GIC version and its driver */
>>> + for (id = __irqchip_acpi_table; id->id[0]; id++) {
>>> + if (gic_version == (u8)id->driver_data) {
>>> + acpi_table_parse(id->id,
>>> + (acpi_tbl_table_handler)id->handler);
>>> + return;
>>> + }
>>> + }
>>> +
>>> + pr_err("No matched driver GIC version %d\n", gic_version);
>>> +}
>>> diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
>>> index 8bd374d..625776c 100644
>>> --- a/include/asm-generic/vmlinux.lds.h
>>> +++ b/include/asm-generic/vmlinux.lds.h
>>> @@ -181,6 +181,18 @@
>>> #define CPUIDLE_METHOD_OF_TABLES() OF_TABLE(CONFIG_CPU_IDLE, cpuidle_method)
>>> #define EARLYCON_OF_TABLES() OF_TABLE(CONFIG_SERIAL_EARLYCON, earlycon)
>>>
>>> +#ifdef CONFIG_ACPI
>>> +#define ACPI_TABLE(name) \
>>> + . = ALIGN(8); \
>>> + VMLINUX_SYMBOL(__##name##_acpi_table) = .; \
>>> + *(__##name##_acpi_table) \
>>> + *(__##name##_acpi_table_end)
>>> +
>>> +#define IRQCHIP_ACPI_MATCH_TABLE() ACPI_TABLE(irqchip)
>>> +#else
>>> +#define IRQCHIP_ACPI_MATCH_TABLE()
>>> +#endif
>>> +
>>> #define KERNEL_DTB() \
>>> STRUCT_ALIGN(); \
>>> VMLINUX_SYMBOL(__dtb_start) = .; \
>>> @@ -516,6 +528,7 @@
>>> CPUIDLE_METHOD_OF_TABLES() \
>>> KERNEL_DTB() \
>>> IRQCHIP_OF_MATCH_TABLE() \
>>> + IRQCHIP_ACPI_MATCH_TABLE() \
>>> EARLYCON_TABLE() \
>>> EARLYCON_OF_TABLES()
>>>
>>> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
>>> index 0820cb1..04dd0bb 100644
>>> --- a/include/linux/acpi.h
>>> +++ b/include/linux/acpi.h
>>> @@ -829,4 +829,20 @@ static inline struct acpi_device *acpi_get_next_child(struct device *dev,
>>>
>>> #endif
>>>
>>> +#ifdef CONFIG_ACPI
>>> +#define ACPI_DECLARE(table, name, table_id, data, fn) \
>>> + static const struct acpi_table_id __acpi_table_##name \
>>> + __used __section(__##table##_acpi_table) \
>>> + = { .id = table_id, \
>>> + .handler = (void *)fn, \
>>> + .driver_data = data }
>>> +#else
>>> +#define ACPI_DECLARE(table, name, table_id, data, fn) \
>>> + static const struct acpi_table_id __acpi_table_##name \
>>> + __attribute__((unused)) \
>>> + = { .id = table_id, \
>>> + .handler = (void *)fn, \
>>> + .driver_data = data }
>>> +#endif
>>> +
>>> #endif /*_LINUX_ACPI_H*/
>>> diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
>>> index 6388873..6b66d3e 100644
>>> --- a/include/linux/irqchip.h
>>> +++ b/include/linux/irqchip.h
>>> @@ -11,6 +11,7 @@
>>> #ifndef _LINUX_IRQCHIP_H
>>> #define _LINUX_IRQCHIP_H
>>>
>>> +#include <linux/acpi.h>
>>> #include <linux/of.h>
>>>
>>> /*
>>> @@ -25,6 +26,18 @@
>>> */
>>> #define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn)
>>>
>>> +/*
>>> + * This macro must be used by the different ARM GIC drivers to declare
>>> + * the association between their version and their initialization function.
>>> + *
>>> + * @name: name that must be unique accross all IRQCHIP_ACPI_DECLARE of the
>>> + * same file.
>>> + * @gic_version: version of GIC
>>> + * @fn: initialization function
>>> + */
>>> +#define IRQCHIP_ACPI_DECLARE(name, gic_version, fn) \
>>> + ACPI_DECLARE(irqchip, name, ACPI_SIG_MADT, gic_version, fn)
>>
>> I don't think this is the right approach. The MADT table has a *huge*
>> number of possible subtables, and none of them is matched by the GIC
>> version.
>>
>> What you *really* want is MADT -> GICD -> GIC type. Your ACPI_DECLARE
>> macro doesn't reflect this at all (you've basically cloned OF, and
>> that's clearly not good enough).
>>
>> This probably require an intermediate matching function, ending up with
>> something like:
>>
>> #define IRQCHIP_ACPI_DECLARE(name, subtable, version, fn) \
>> ACPI_DECLARE(irqchip, name, ACPI_SIG_MADT, match_madt_subtable,\
>> subtable, version, fn)
>>
>> where match_madt_subtable is going to check that a given subtable is
>> really suitable for a given irqchip. None of that should be GIC
>> specific, really.
>
> I'm little confused here, in the previous patch, the gic version is
> stored, so we only need to match the GIC driver with the gic version.
>
> In the GIC dirver itself, we will match the madt subtable to find
> information we need to init the GIC, so I'm not sure why
> match_madt_subtable in the ACPI_DECLARE, I think I missed something,
> please correct me.
What you're missing is that it should be possible to use
IRQCHIP_ACPI_DECLARE with something that is *not* a GIC. It shouldn't be
GIC specific in any way.
You must have a generic way of describing a match in a table by naming
one of its structures, and possibly a type value inside this structures.
I want to be able to write something like:
IRQCHIP_ACPI_DECLARE(ioapic, ACPI_IOAPIC, 0, ioacpi_acpi_probe);
where ACPI_IOAPIC is 1 (the type for the IOAPIC structure in the MADT
table).
For GICv3, I want to be able to write:
IRQCHIP_ACPI_DECLARE(gicv3, ACPI_GICD, ACPI_GICD_GICV3, \
gicv3_acpi_probe);
where ACPI_GICD is 0xC, and ACPI_GICD_GICV3 is 3.
Do you see what I'm aiming for? We follow the spec, strictly the spec,
but all the spec. No shortcut that only ends up matching the GIC in MADT.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-07-29 12:20 +0200 |
| Subject | [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization |
| Message-ID | <pRwCS-59z-17@gated-at.bofh.it> |
| In reply to | #1195003 |
From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
With the refator of gic_of_init(), GICv3/4 can be initialized
by gic_init_bases() with gic distributor base address and gic
redistributor region(s).
So get the redistributor region base addresses from MADT GIC
redistributor subtable, and the distributor base address from
GICD subtable to init GICv3 irqchip in ACPI way.
Note: GIC redistributor base address may also be provided in
GICC structures on systems supporting GICv3 and above if the GIC
Redistributors are not in the always-on power domain, this
patch didn't implement such feature yet.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
[hj: Rework this patch and fix multi issues]
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/irqchip/irq-gic-v3.c | 174 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 169 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index c0b96c6..ebc5604 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -15,6 +15,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/cpu_pm.h>
#include <linux/delay.h>
@@ -25,6 +26,7 @@
#include <linux/percpu.h>
#include <linux/slab.h>
+#include <linux/irqchip/arm-gic-acpi.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <asm/cputype.h>
@@ -802,7 +804,8 @@ static int __init gic_init_bases(void __iomem *dist_base,
set_handle_irq(gic_handle_irq);
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
- its_init(domain_token, &gic_data.rdists, gic_data.domain);
+ its_init(irq_domain_token_to_of_node(domain_token),
+ &gic_data.rdists, gic_data.domain);
gic_smp_init();
gic_dist_init();
@@ -818,6 +821,16 @@ out_free:
return err;
}
+static int __init detect_distributor(void __iomem *dist_base)
+{
+ u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
+
+ if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
+ return -ENODEV;
+
+ return 0;
+}
+
#ifdef CONFIG_OF
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
{
@@ -825,7 +838,6 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
struct redist_region *rdist_regs;
u64 redist_stride;
u32 nr_redist_regions;
- u32 reg;
int err, i;
dist_base = of_iomap(node, 0);
@@ -835,11 +847,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
return -ENXIO;
}
- reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
- if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
+ err = detect_distributor(dist_base);
+ if (err) {
pr_err("%s: no distributor detected, giving up\n",
node->full_name);
- err = -ENODEV;
goto out_unmap_dist;
}
@@ -887,3 +898,156 @@ out_unmap_dist:
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
#endif
+
+#ifdef CONFIG_ACPI
+static struct redist_region *redist_regs __initdata;
+static u32 nr_redist_regions __initdata;
+static phys_addr_t dist_phys_base __initdata;
+
+static int __init
+gic_acpi_register_redist(u64 phys_base, u64 size)
+{
+ struct redist_region *redist_regs_new;
+ void __iomem *redist_base;
+
+ redist_regs_new = krealloc(redist_regs,
+ sizeof(*redist_regs) * (nr_redist_regions + 1),
+ GFP_KERNEL);
+ if (!redist_regs_new) {
+ pr_err("Couldn't allocate resource for GICR region\n");
+ return -ENOMEM;
+ }
+
+ redist_regs = redist_regs_new;
+
+ redist_base = ioremap(phys_base, size);
+ if (!redist_base) {
+ pr_err("Couldn't map GICR region @%llx\n", phys_base);
+ return -ENOMEM;
+ }
+
+ redist_regs[nr_redist_regions].phys_base = phys_base;
+ redist_regs[nr_redist_regions].redist_base = redist_base;
+ nr_redist_regions++;
+ return 0;
+}
+
+static int __init
+gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_redistributor *redist;
+
+ if (BAD_MADT_ENTRY(header, end))
+ return -EINVAL;
+
+ redist = (struct acpi_madt_generic_redistributor *)header;
+ if (!redist->base_address)
+ return -EINVAL;
+
+ return gic_acpi_register_redist(redist->base_address, redist->length);
+}
+
+static int __init
+gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_distributor *dist;
+
+ dist = (struct acpi_madt_generic_distributor *)header;
+
+ if (BAD_MADT_ENTRY(dist, end))
+ return -EINVAL;
+
+ dist_phys_base = dist->base_address;
+ return 0;
+}
+
+static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
+ u32 gsi, unsigned int irq_type)
+{
+ /*
+ * Encode GSI and triggering information the way the GIC likes
+ * them.
+ */
+ if (WARN_ON(gsi < 16))
+ return -EINVAL;
+
+ if (gsi >= 32) {
+ data->param[0] = 0; /* SPI */
+ data->param[1] = gsi - 32;
+ data->param[2] = irq_type;
+ } else {
+ data->param[0] = 1; /* PPI */
+ data->param[1] = gsi - 16;
+ data->param[2] = 0xff << 4 | irq_type;
+ }
+
+ data->param_count = 3;
+
+ return 0;
+}
+
+static int __init
+gic_acpi_init(struct acpi_table_header *table)
+{
+ int count, i, err = 0;
+ void __iomem *dist_base;
+
+ /* Get distributor base address */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_distributor, table,
+ ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
+ if (count <= 0) {
+ pr_err("No valid GICD entry exist\n");
+ return -EINVAL;
+ } else if (count > 1) {
+ pr_err("More than one GICD entry detected\n");
+ return -EINVAL;
+ }
+
+ dist_base = ioremap(dist_phys_base, ACPI_GICV3_DIST_MEM_SIZE);
+ if (!dist_base) {
+ pr_err("Unable to map GICD registers\n");
+ return -ENOMEM;
+ }
+
+ err = detect_distributor(dist_base);
+ if (err) {
+ pr_err("No distributor detected at @%p, giving up", dist_base);
+ goto out_dist_unmap;
+ }
+
+ /* Collect redistributor base addresses */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_redist, table,
+ ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
+ if (count <= 0) {
+ pr_info("No valid GICR entries exist\n");
+ err = -EINVAL;
+ goto out_redist_unmap;
+ }
+
+ err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
+ (void *)ACPI_IRQ_MODEL_GIC);
+ if (err)
+ goto out_redist_unmap;
+
+ acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
+ gic_acpi_gsi_desc_populate);
+ return 0;
+
+out_redist_unmap:
+ for (i = 0; i < nr_redist_regions; i++)
+ if (redist_regs[i].redist_base)
+ iounmap(redist_regs[i].redist_base);
+ kfree(redist_regs);
+out_dist_unmap:
+ iounmap(dist_base);
+ return err;
+}
+IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_GIC_VERSION_V3, gic_acpi_init);
+IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_GIC_VERSION_V4, gic_acpi_init);
+#endif
--
1.9.1
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-04 15:20 +0200 |
| Subject | Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization |
| Message-ID | <pTKim-3aR-11@gated-at.bofh.it> |
| In reply to | #1195017 |
On 29/07/15 11:08, Hanjun Guo wrote:
> From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>
> With the refator of gic_of_init(), GICv3/4 can be initialized
> by gic_init_bases() with gic distributor base address and gic
> redistributor region(s).
>
> So get the redistributor region base addresses from MADT GIC
> redistributor subtable, and the distributor base address from
> GICD subtable to init GICv3 irqchip in ACPI way.
>
> Note: GIC redistributor base address may also be provided in
> GICC structures on systems supporting GICv3 and above if the GIC
> Redistributors are not in the always-on power domain, this
> patch didn't implement such feature yet.
>
> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
> [hj: Rework this patch and fix multi issues]
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> ---
> drivers/irqchip/irq-gic-v3.c | 174 +++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 169 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index c0b96c6..ebc5604 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -15,6 +15,7 @@
> * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#include <linux/acpi.h>
> #include <linux/cpu.h>
> #include <linux/cpu_pm.h>
> #include <linux/delay.h>
> @@ -25,6 +26,7 @@
> #include <linux/percpu.h>
> #include <linux/slab.h>
>
> +#include <linux/irqchip/arm-gic-acpi.h>
> #include <linux/irqchip/arm-gic-v3.h>
>
> #include <asm/cputype.h>
> @@ -802,7 +804,8 @@ static int __init gic_init_bases(void __iomem *dist_base,
> set_handle_irq(gic_handle_irq);
>
> if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
> - its_init(domain_token, &gic_data.rdists, gic_data.domain);
> + its_init(irq_domain_token_to_of_node(domain_token),
> + &gic_data.rdists, gic_data.domain);
This doesn't make much sense. The first parameter to its_init is indeed
supposed to be an of_node, but what is the point of calling its_init if
you *know* you don't have the necessary topological information to parse
the firmware tables?
I don't see *any* code that is going to parse the ITS table in this
series, so please don't call its_init passing a NULL pointer to it. This
is just gross.
>
> gic_smp_init();
> gic_dist_init();
> @@ -818,6 +821,16 @@ out_free:
> return err;
> }
>
> +static int __init detect_distributor(void __iomem *dist_base)
We do have a naming convention in this file. All functions start with gic_.
> +{
> + u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
> +
> + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
> + return -ENODEV;
> +
> + return 0;
> +}
This function doesn't detect anything, it validates that we have
something sensible. Please rename it to gic_validate_dist_version, or
something similar.
> +
> #ifdef CONFIG_OF
> static int __init gic_of_init(struct device_node *node, struct device_node *parent)
> {
> @@ -825,7 +838,6 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
> struct redist_region *rdist_regs;
> u64 redist_stride;
> u32 nr_redist_regions;
> - u32 reg;
> int err, i;
>
> dist_base = of_iomap(node, 0);
> @@ -835,11 +847,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
> return -ENXIO;
> }
>
> - reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
> - if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
> + err = detect_distributor(dist_base);
> + if (err) {
> pr_err("%s: no distributor detected, giving up\n",
> node->full_name);
> - err = -ENODEV;
> goto out_unmap_dist;
> }
>
> @@ -887,3 +898,156 @@ out_unmap_dist:
>
> IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
> #endif
> +
> +#ifdef CONFIG_ACPI
> +static struct redist_region *redist_regs __initdata;
> +static u32 nr_redist_regions __initdata;
> +static phys_addr_t dist_phys_base __initdata;
> +
> +static int __init
> +gic_acpi_register_redist(u64 phys_base, u64 size)
A physical address must use phys_addr_t.
> +{
> + struct redist_region *redist_regs_new;
> + void __iomem *redist_base;
> +
> + redist_regs_new = krealloc(redist_regs,
> + sizeof(*redist_regs) * (nr_redist_regions + 1),
> + GFP_KERNEL);
NAK. If you have multiple regions, you count them, you allocate the
right number of regions. This will be far more efficient than doing this
realloc dance. It is not like we're not parsing the tables a zillion
times already. Doing it one more time won't hurt.
> + if (!redist_regs_new) {
> + pr_err("Couldn't allocate resource for GICR region\n");
> + return -ENOMEM;
> + }
> +
> + redist_regs = redist_regs_new;
> +
> + redist_base = ioremap(phys_base, size);
> + if (!redist_base) {
> + pr_err("Couldn't map GICR region @%llx\n", phys_base);
> + return -ENOMEM;
> + }
> +
> + redist_regs[nr_redist_regions].phys_base = phys_base;
> + redist_regs[nr_redist_regions].redist_base = redist_base;
> + nr_redist_regions++;
> + return 0;
> +}
> +
> +static int __init
> +gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_generic_redistributor *redist;
> +
> + if (BAD_MADT_ENTRY(header, end))
> + return -EINVAL;
> +
> + redist = (struct acpi_madt_generic_redistributor *)header;
> + if (!redist->base_address)
> + return -EINVAL;
> +
> + return gic_acpi_register_redist(redist->base_address, redist->length);
> +}
> +
> +static int __init
> +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
How many versions of gic_acpi_parse_madt_distributor are we going to
get? Why isn't the ACPI parsing in a common file? Why do I have to read
the same code on and on until my eyes bleed?
> + struct acpi_madt_generic_distributor *dist;
> +
> + dist = (struct acpi_madt_generic_distributor *)header;
> +
> + if (BAD_MADT_ENTRY(dist, end))
> + return -EINVAL;
> +
> + dist_phys_base = dist->base_address;
> + return 0;
> +}
> +
> +static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
> + u32 gsi, unsigned int irq_type)
> +{
> + /*
> + * Encode GSI and triggering information the way the GIC likes
> + * them.
> + */
> + if (WARN_ON(gsi < 16))
> + return -EINVAL;
> +
> + if (gsi >= 32) {
> + data->param[0] = 0; /* SPI */
> + data->param[1] = gsi - 32;
> + data->param[2] = irq_type;
> + } else {
> + data->param[0] = 1; /* PPI */
> + data->param[1] = gsi - 16;
> + data->param[2] = 0xff << 4 | irq_type;
> + }
> +
> + data->param_count = 3;
> +
> + return 0;
> +}
> +
> +static int __init
> +gic_acpi_init(struct acpi_table_header *table)
> +{
> + int count, i, err = 0;
> + void __iomem *dist_base;
> +
> + /* Get distributor base address */
> + count = acpi_parse_entries(ACPI_SIG_MADT,
> + sizeof(struct acpi_table_madt),
> + gic_acpi_parse_madt_distributor, table,
> + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
> + if (count <= 0) {
> + pr_err("No valid GICD entry exist\n");
> + return -EINVAL;
> + } else if (count > 1) {
> + pr_err("More than one GICD entry detected\n");
> + return -EINVAL;
> + }
> +
> + dist_base = ioremap(dist_phys_base, ACPI_GICV3_DIST_MEM_SIZE);
> + if (!dist_base) {
> + pr_err("Unable to map GICD registers\n");
> + return -ENOMEM;
> + }
> +
> + err = detect_distributor(dist_base);
> + if (err) {
> + pr_err("No distributor detected at @%p, giving up", dist_base);
> + goto out_dist_unmap;
> + }
> +
> + /* Collect redistributor base addresses */
> + count = acpi_parse_entries(ACPI_SIG_MADT,
> + sizeof(struct acpi_table_madt),
> + gic_acpi_parse_madt_redist, table,
> + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
> + if (count <= 0) {
> + pr_info("No valid GICR entries exist\n");
> + err = -EINVAL;
> + goto out_redist_unmap;
> + }
> +
> + err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
> + (void *)ACPI_IRQ_MODEL_GIC);
There is no other global identifier for GICv3? It feels a bit weird to
use the same ID as GICv2 (though probably not harmful as you can't have
both as the same time). What are you planning to use for the ITS then?
You must make sure you have a global namespace.
> + if (err)
> + goto out_redist_unmap;
> +
> + acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
> + gic_acpi_gsi_desc_populate);
> + return 0;
> +
> +out_redist_unmap:
> + for (i = 0; i < nr_redist_regions; i++)
> + if (redist_regs[i].redist_base)
> + iounmap(redist_regs[i].redist_base);
> + kfree(redist_regs);
> +out_dist_unmap:
> + iounmap(dist_base);
> + return err;
> +}
> +IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_GIC_VERSION_V3, gic_acpi_init);
> +IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_GIC_VERSION_V4, gic_acpi_init);
As mentioned before, this doesn't work.
> +#endif
>
Thanks,
M.
--
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[toc] | [prev] | [next] | [standalone]
| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-08-05 16:10 +0200 |
| Subject | Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization |
| Message-ID | <pU7yh-3zf-9@gated-at.bofh.it> |
| In reply to | #1199823 |
On 08/04/2015 09:17 PM, Marc Zyngier wrote:
> On 29/07/15 11:08, Hanjun Guo wrote:
>> From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>>
>> With the refator of gic_of_init(), GICv3/4 can be initialized
>> by gic_init_bases() with gic distributor base address and gic
>> redistributor region(s).
>>
>> So get the redistributor region base addresses from MADT GIC
>> redistributor subtable, and the distributor base address from
>> GICD subtable to init GICv3 irqchip in ACPI way.
>>
>> Note: GIC redistributor base address may also be provided in
>> GICC structures on systems supporting GICv3 and above if the GIC
>> Redistributors are not in the always-on power domain, this
>> patch didn't implement such feature yet.
>>
>> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>> [hj: Rework this patch and fix multi issues]
>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>> ---
>> drivers/irqchip/irq-gic-v3.c | 174 +++++++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 169 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>> index c0b96c6..ebc5604 100644
>> --- a/drivers/irqchip/irq-gic-v3.c
>> +++ b/drivers/irqchip/irq-gic-v3.c
>> @@ -15,6 +15,7 @@
>> * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> */
>>
>> +#include <linux/acpi.h>
>> #include <linux/cpu.h>
>> #include <linux/cpu_pm.h>
>> #include <linux/delay.h>
>> @@ -25,6 +26,7 @@
>> #include <linux/percpu.h>
>> #include <linux/slab.h>
>>
>> +#include <linux/irqchip/arm-gic-acpi.h>
>> #include <linux/irqchip/arm-gic-v3.h>
>>
>> #include <asm/cputype.h>
>> @@ -802,7 +804,8 @@ static int __init gic_init_bases(void __iomem *dist_base,
>> set_handle_irq(gic_handle_irq);
>>
>> if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
>> - its_init(domain_token, &gic_data.rdists, gic_data.domain);
>> + its_init(irq_domain_token_to_of_node(domain_token),
>> + &gic_data.rdists, gic_data.domain);
>
> This doesn't make much sense. The first parameter to its_init is indeed
> supposed to be an of_node, but what is the point of calling its_init if
> you *know* you don't have the necessary topological information to parse
> the firmware tables?
>
> I don't see *any* code that is going to parse the ITS table in this
> series, so please don't call its_init passing a NULL pointer to it. This
> is just gross.
OK, the ITS ACPI code is in later patch which combined with IORT. How
about moving it to the GIC of init code temporary?
>
>>
>> gic_smp_init();
>> gic_dist_init();
>> @@ -818,6 +821,16 @@ out_free:
>> return err;
>> }
>>
>> +static int __init detect_distributor(void __iomem *dist_base)
>
> We do have a naming convention in this file. All functions start with gic_.
>
>> +{
>> + u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
>> +
>> + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>
> This function doesn't detect anything, it validates that we have
> something sensible. Please rename it to gic_validate_dist_version, or
> something similar.
Ok.
>
>> +
>> #ifdef CONFIG_OF
>> static int __init gic_of_init(struct device_node *node, struct device_node *parent)
>> {
>> @@ -825,7 +838,6 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
>> struct redist_region *rdist_regs;
>> u64 redist_stride;
>> u32 nr_redist_regions;
>> - u32 reg;
>> int err, i;
>>
>> dist_base = of_iomap(node, 0);
>> @@ -835,11 +847,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
>> return -ENXIO;
>> }
>>
>> - reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
>> - if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
>> + err = detect_distributor(dist_base);
>> + if (err) {
>> pr_err("%s: no distributor detected, giving up\n",
>> node->full_name);
>> - err = -ENODEV;
>> goto out_unmap_dist;
>> }
>>
>> @@ -887,3 +898,156 @@ out_unmap_dist:
>>
>> IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
>> #endif
>> +
>> +#ifdef CONFIG_ACPI
>> +static struct redist_region *redist_regs __initdata;
>> +static u32 nr_redist_regions __initdata;
>> +static phys_addr_t dist_phys_base __initdata;
>> +
>> +static int __init
>> +gic_acpi_register_redist(u64 phys_base, u64 size)
>
> A physical address must use phys_addr_t.
OK.
>
>> +{
>> + struct redist_region *redist_regs_new;
>> + void __iomem *redist_base;
>> +
>> + redist_regs_new = krealloc(redist_regs,
>> + sizeof(*redist_regs) * (nr_redist_regions + 1),
>> + GFP_KERNEL);
>
> NAK. If you have multiple regions, you count them, you allocate the
> right number of regions. This will be far more efficient than doing this
> realloc dance. It is not like we're not parsing the tables a zillion
> times already. Doing it one more time won't hurt.
Agreed, will update in next version.
>
>> + if (!redist_regs_new) {
>> + pr_err("Couldn't allocate resource for GICR region\n");
>> + return -ENOMEM;
>> + }
>> +
>> + redist_regs = redist_regs_new;
>> +
>> + redist_base = ioremap(phys_base, size);
>> + if (!redist_base) {
>> + pr_err("Couldn't map GICR region @%llx\n", phys_base);
>> + return -ENOMEM;
>> + }
>> +
>> + redist_regs[nr_redist_regions].phys_base = phys_base;
>> + redist_regs[nr_redist_regions].redist_base = redist_base;
>> + nr_redist_regions++;
>> + return 0;
>> +}
>> +
>> +static int __init
>> +gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_generic_redistributor *redist;
>> +
>> + if (BAD_MADT_ENTRY(header, end))
>> + return -EINVAL;
>> +
>> + redist = (struct acpi_madt_generic_redistributor *)header;
>> + if (!redist->base_address)
>> + return -EINVAL;
>> +
>> + return gic_acpi_register_redist(redist->base_address, redist->length);
>> +}
>> +
>> +static int __init
>> +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
>> + const unsigned long end)
>> +{
>
> How many versions of gic_acpi_parse_madt_distributor are we going to
> get? Why isn't the ACPI parsing in a common file? Why do I have to read
> the same code on and on until my eyes bleed?
I will try to move it to common file irq-gic-acpi.c.
>
>> + struct acpi_madt_generic_distributor *dist;
>> +
>> + dist = (struct acpi_madt_generic_distributor *)header;
>> +
>> + if (BAD_MADT_ENTRY(dist, end))
>> + return -EINVAL;
>> +
>> + dist_phys_base = dist->base_address;
>> + return 0;
>> +}
>> +
>> +static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
>> + u32 gsi, unsigned int irq_type)
>> +{
>> + /*
>> + * Encode GSI and triggering information the way the GIC likes
>> + * them.
>> + */
>> + if (WARN_ON(gsi < 16))
>> + return -EINVAL;
>> +
>> + if (gsi >= 32) {
>> + data->param[0] = 0; /* SPI */
>> + data->param[1] = gsi - 32;
>> + data->param[2] = irq_type;
>> + } else {
>> + data->param[0] = 1; /* PPI */
>> + data->param[1] = gsi - 16;
>> + data->param[2] = 0xff << 4 | irq_type;
>> + }
>> +
>> + data->param_count = 3;
>> +
>> + return 0;
>> +}
>> +
>> +static int __init
>> +gic_acpi_init(struct acpi_table_header *table)
>> +{
>> + int count, i, err = 0;
>> + void __iomem *dist_base;
>> +
>> + /* Get distributor base address */
>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>> + sizeof(struct acpi_table_madt),
>> + gic_acpi_parse_madt_distributor, table,
>> + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
>> + if (count <= 0) {
>> + pr_err("No valid GICD entry exist\n");
>> + return -EINVAL;
>> + } else if (count > 1) {
>> + pr_err("More than one GICD entry detected\n");
>> + return -EINVAL;
>> + }
>> +
>> + dist_base = ioremap(dist_phys_base, ACPI_GICV3_DIST_MEM_SIZE);
>> + if (!dist_base) {
>> + pr_err("Unable to map GICD registers\n");
>> + return -ENOMEM;
>> + }
>> +
>> + err = detect_distributor(dist_base);
>> + if (err) {
>> + pr_err("No distributor detected at @%p, giving up", dist_base);
>> + goto out_dist_unmap;
>> + }
>> +
>> + /* Collect redistributor base addresses */
>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>> + sizeof(struct acpi_table_madt),
>> + gic_acpi_parse_madt_redist, table,
>> + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
>> + if (count <= 0) {
>> + pr_info("No valid GICR entries exist\n");
>> + err = -EINVAL;
>> + goto out_redist_unmap;
>> + }
>> +
>> + err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
>> + (void *)ACPI_IRQ_MODEL_GIC);
>
> There is no other global identifier for GICv3? It feels a bit weird to
> use the same ID as GICv2 (though probably not harmful as you can't have
> both as the same time). What are you planning to use for the ITS then?
> You must make sure you have a global namespace.
I will use the ITS physical base address as the token for ITS, maybe I
can use the GICD physical base address here instead?
>
>> + if (err)
>> + goto out_redist_unmap;
>> +
>> + acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
>> + gic_acpi_gsi_desc_populate);
>> + return 0;
>> +
>> +out_redist_unmap:
>> + for (i = 0; i < nr_redist_regions; i++)
>> + if (redist_regs[i].redist_base)
>> + iounmap(redist_regs[i].redist_base);
>> + kfree(redist_regs);
>> +out_dist_unmap:
>> + iounmap(dist_base);
>> + return err;
>> +}
>> +IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_GIC_VERSION_V3, gic_acpi_init);
>> +IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_GIC_VERSION_V4, gic_acpi_init);
>
> As mentioned before, this doesn't work.
hmm, I think we need more discussion for this one, but we need to match
V4 for GICv3 drivers, and everything will be the same in the dirver
as I said before.
Thanks
Hanjun
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-06 18:50 +0200 |
| Subject | Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization |
| Message-ID | <pUwwG-6kc-17@gated-at.bofh.it> |
| In reply to | #1200811 |
On 05/08/15 15:00, Hanjun Guo wrote:
> On 08/04/2015 09:17 PM, Marc Zyngier wrote:
>> On 29/07/15 11:08, Hanjun Guo wrote:
>>> From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>>>
>>> With the refator of gic_of_init(), GICv3/4 can be initialized
>>> by gic_init_bases() with gic distributor base address and gic
>>> redistributor region(s).
>>>
>>> So get the redistributor region base addresses from MADT GIC
>>> redistributor subtable, and the distributor base address from
>>> GICD subtable to init GICv3 irqchip in ACPI way.
>>>
>>> Note: GIC redistributor base address may also be provided in
>>> GICC structures on systems supporting GICv3 and above if the GIC
>>> Redistributors are not in the always-on power domain, this
>>> patch didn't implement such feature yet.
>>>
>>> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>>> [hj: Rework this patch and fix multi issues]
>>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>>> ---
>>> drivers/irqchip/irq-gic-v3.c | 174 +++++++++++++++++++++++++++++++++++++++++--
>>> 1 file changed, 169 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>>> index c0b96c6..ebc5604 100644
>>> --- a/drivers/irqchip/irq-gic-v3.c
>>> +++ b/drivers/irqchip/irq-gic-v3.c
>>> @@ -15,6 +15,7 @@
>>> * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>> */
>>>
>>> +#include <linux/acpi.h>
>>> #include <linux/cpu.h>
>>> #include <linux/cpu_pm.h>
>>> #include <linux/delay.h>
>>> @@ -25,6 +26,7 @@
>>> #include <linux/percpu.h>
>>> #include <linux/slab.h>
>>>
>>> +#include <linux/irqchip/arm-gic-acpi.h>
>>> #include <linux/irqchip/arm-gic-v3.h>
>>>
>>> #include <asm/cputype.h>
>>> @@ -802,7 +804,8 @@ static int __init gic_init_bases(void __iomem *dist_base,
>>> set_handle_irq(gic_handle_irq);
>>>
>>> if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
>>> - its_init(domain_token, &gic_data.rdists, gic_data.domain);
>>> + its_init(irq_domain_token_to_of_node(domain_token),
>>> + &gic_data.rdists, gic_data.domain);
>>
>> This doesn't make much sense. The first parameter to its_init is indeed
>> supposed to be an of_node, but what is the point of calling its_init if
>> you *know* you don't have the necessary topological information to parse
>> the firmware tables?
>>
>> I don't see *any* code that is going to parse the ITS table in this
>> series, so please don't call its_init passing a NULL pointer to it. This
>> is just gross.
>
> OK, the ITS ACPI code is in later patch which combined with IORT. How
> about moving it to the GIC of init code temporary?
Just don't call its_init if irq_domain_token_to_of_node(domain_token) is
NULL. But don't call it with a NULL parameter.
>>
>>>
>>> gic_smp_init();
>>> gic_dist_init();
>>> @@ -818,6 +821,16 @@ out_free:
>>> return err;
>>> }
>>>
>>> +static int __init detect_distributor(void __iomem *dist_base)
>>
>> We do have a naming convention in this file. All functions start with gic_.
>>
>>> +{
>>> + u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
>>> +
>>> + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
>>> + return -ENODEV;
>>> +
>>> + return 0;
>>> +}
>>
>> This function doesn't detect anything, it validates that we have
>> something sensible. Please rename it to gic_validate_dist_version, or
>> something similar.
>
> Ok.
>
>>
>>> +
>>> #ifdef CONFIG_OF
>>> static int __init gic_of_init(struct device_node *node, struct device_node *parent)
>>> {
>>> @@ -825,7 +838,6 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
>>> struct redist_region *rdist_regs;
>>> u64 redist_stride;
>>> u32 nr_redist_regions;
>>> - u32 reg;
>>> int err, i;
>>>
>>> dist_base = of_iomap(node, 0);
>>> @@ -835,11 +847,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
>>> return -ENXIO;
>>> }
>>>
>>> - reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
>>> - if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
>>> + err = detect_distributor(dist_base);
>>> + if (err) {
>>> pr_err("%s: no distributor detected, giving up\n",
>>> node->full_name);
>>> - err = -ENODEV;
>>> goto out_unmap_dist;
>>> }
>>>
>>> @@ -887,3 +898,156 @@ out_unmap_dist:
>>>
>>> IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
>>> #endif
>>> +
>>> +#ifdef CONFIG_ACPI
>>> +static struct redist_region *redist_regs __initdata;
>>> +static u32 nr_redist_regions __initdata;
>>> +static phys_addr_t dist_phys_base __initdata;
>>> +
>>> +static int __init
>>> +gic_acpi_register_redist(u64 phys_base, u64 size)
>>
>> A physical address must use phys_addr_t.
>
> OK.
>
>>
>>> +{
>>> + struct redist_region *redist_regs_new;
>>> + void __iomem *redist_base;
>>> +
>>> + redist_regs_new = krealloc(redist_regs,
>>> + sizeof(*redist_regs) * (nr_redist_regions + 1),
>>> + GFP_KERNEL);
>>
>> NAK. If you have multiple regions, you count them, you allocate the
>> right number of regions. This will be far more efficient than doing this
>> realloc dance. It is not like we're not parsing the tables a zillion
>> times already. Doing it one more time won't hurt.
>
> Agreed, will update in next version.
>
>>
>>> + if (!redist_regs_new) {
>>> + pr_err("Couldn't allocate resource for GICR region\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + redist_regs = redist_regs_new;
>>> +
>>> + redist_base = ioremap(phys_base, size);
>>> + if (!redist_base) {
>>> + pr_err("Couldn't map GICR region @%llx\n", phys_base);
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + redist_regs[nr_redist_regions].phys_base = phys_base;
>>> + redist_regs[nr_redist_regions].redist_base = redist_base;
>>> + nr_redist_regions++;
>>> + return 0;
>>> +}
>>> +
>>> +static int __init
>>> +gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
>>> + const unsigned long end)
>>> +{
>>> + struct acpi_madt_generic_redistributor *redist;
>>> +
>>> + if (BAD_MADT_ENTRY(header, end))
>>> + return -EINVAL;
>>> +
>>> + redist = (struct acpi_madt_generic_redistributor *)header;
>>> + if (!redist->base_address)
>>> + return -EINVAL;
>>> +
>>> + return gic_acpi_register_redist(redist->base_address, redist->length);
>>> +}
>>> +
>>> +static int __init
>>> +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
>>> + const unsigned long end)
>>> +{
>>
>> How many versions of gic_acpi_parse_madt_distributor are we going to
>> get? Why isn't the ACPI parsing in a common file? Why do I have to read
>> the same code on and on until my eyes bleed?
>
> I will try to move it to common file irq-gic-acpi.c.
>
>>
>>> + struct acpi_madt_generic_distributor *dist;
>>> +
>>> + dist = (struct acpi_madt_generic_distributor *)header;
>>> +
>>> + if (BAD_MADT_ENTRY(dist, end))
>>> + return -EINVAL;
>>> +
>>> + dist_phys_base = dist->base_address;
>>> + return 0;
>>> +}
>>> +
>>> +static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
>>> + u32 gsi, unsigned int irq_type)
>>> +{
>>> + /*
>>> + * Encode GSI and triggering information the way the GIC likes
>>> + * them.
>>> + */
>>> + if (WARN_ON(gsi < 16))
>>> + return -EINVAL;
>>> +
>>> + if (gsi >= 32) {
>>> + data->param[0] = 0; /* SPI */
>>> + data->param[1] = gsi - 32;
>>> + data->param[2] = irq_type;
>>> + } else {
>>> + data->param[0] = 1; /* PPI */
>>> + data->param[1] = gsi - 16;
>>> + data->param[2] = 0xff << 4 | irq_type;
>>> + }
>>> +
>>> + data->param_count = 3;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int __init
>>> +gic_acpi_init(struct acpi_table_header *table)
>>> +{
>>> + int count, i, err = 0;
>>> + void __iomem *dist_base;
>>> +
>>> + /* Get distributor base address */
>>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>>> + sizeof(struct acpi_table_madt),
>>> + gic_acpi_parse_madt_distributor, table,
>>> + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
>>> + if (count <= 0) {
>>> + pr_err("No valid GICD entry exist\n");
>>> + return -EINVAL;
>>> + } else if (count > 1) {
>>> + pr_err("More than one GICD entry detected\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + dist_base = ioremap(dist_phys_base, ACPI_GICV3_DIST_MEM_SIZE);
>>> + if (!dist_base) {
>>> + pr_err("Unable to map GICD registers\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + err = detect_distributor(dist_base);
>>> + if (err) {
>>> + pr_err("No distributor detected at @%p, giving up", dist_base);
>>> + goto out_dist_unmap;
>>> + }
>>> +
>>> + /* Collect redistributor base addresses */
>>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>>> + sizeof(struct acpi_table_madt),
>>> + gic_acpi_parse_madt_redist, table,
>>> + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
>>> + if (count <= 0) {
>>> + pr_info("No valid GICR entries exist\n");
>>> + err = -EINVAL;
>>> + goto out_redist_unmap;
>>> + }
>>> +
>>> + err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
>>> + (void *)ACPI_IRQ_MODEL_GIC);
>>
>> There is no other global identifier for GICv3? It feels a bit weird to
>> use the same ID as GICv2 (though probably not harmful as you can't have
>> both as the same time). What are you planning to use for the ITS then?
>> You must make sure you have a global namespace.
>
> I will use the ITS physical base address as the token for ITS, maybe I
> can use the GICD physical base address here instead?
That should be fine as long as the physical address cannot be
interpreted as a kernel address. Which is still a bit dodgy. I'd be more
happy if you had a proper namespace.
>>
>>> + if (err)
>>> + goto out_redist_unmap;
>>> +
>>> + acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
>>> + gic_acpi_gsi_desc_populate);
>>> + return 0;
>>> +
>>> +out_redist_unmap:
>>> + for (i = 0; i < nr_redist_regions; i++)
>>> + if (redist_regs[i].redist_base)
>>> + iounmap(redist_regs[i].redist_base);
>>> + kfree(redist_regs);
>>> +out_dist_unmap:
>>> + iounmap(dist_base);
>>> + return err;
>>> +}
>>> +IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_GIC_VERSION_V3, gic_acpi_init);
>>> +IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_GIC_VERSION_V4, gic_acpi_init);
>>
>> As mentioned before, this doesn't work.
>
> hmm, I think we need more discussion for this one, but we need to match
> V4 for GICv3 drivers, and everything will be the same in the dirver
> as I said before.
And as I said before, you don't need to distinguish v3 from v4 in the
ACPI code. Matching GICv3 is enough.
Thanks,
M.
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| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-08-11 09:30 +0200 |
| Subject | Re: [PATCH v4 06/10] irqchip / GICv3: Add ACPI support for GICv3+ initialization |
| Message-ID | <pWcau-6DQ-7@gated-at.bofh.it> |
| In reply to | #1201904 |
Hi Marc,
On 08/07/2015 12:42 AM, Marc Zyngier wrote:
> On 05/08/15 15:00, Hanjun Guo wrote:
>> On 08/04/2015 09:17 PM, Marc Zyngier wrote:
>>> On 29/07/15 11:08, Hanjun Guo wrote:
>>>> From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>>>>
>>>> With the refator of gic_of_init(), GICv3/4 can be initialized
>>>> by gic_init_bases() with gic distributor base address and gic
>>>> redistributor region(s).
>>>>
>>>> So get the redistributor region base addresses from MADT GIC
>>>> redistributor subtable, and the distributor base address from
>>>> GICD subtable to init GICv3 irqchip in ACPI way.
>>>>
>>>> Note: GIC redistributor base address may also be provided in
>>>> GICC structures on systems supporting GICv3 and above if the GIC
>>>> Redistributors are not in the always-on power domain, this
>>>> patch didn't implement such feature yet.
>>>>
>>>> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
>>>> [hj: Rework this patch and fix multi issues]
>>>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>>>> ---
>>>> drivers/irqchip/irq-gic-v3.c | 174 +++++++++++++++++++++++++++++++++++++++++--
>>>> 1 file changed, 169 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>>>> index c0b96c6..ebc5604 100644
>>>> --- a/drivers/irqchip/irq-gic-v3.c
>>>> +++ b/drivers/irqchip/irq-gic-v3.c
>>>> @@ -15,6 +15,7 @@
>>>> * along with this program. If not, see <http://www.gnu.org/licenses/>.
>>>> */
>>>>
>>>> +#include <linux/acpi.h>
>>>> #include <linux/cpu.h>
>>>> #include <linux/cpu_pm.h>
>>>> #include <linux/delay.h>
>>>> @@ -25,6 +26,7 @@
>>>> #include <linux/percpu.h>
>>>> #include <linux/slab.h>
>>>>
>>>> +#include <linux/irqchip/arm-gic-acpi.h>
>>>> #include <linux/irqchip/arm-gic-v3.h>
>>>>
>>>> #include <asm/cputype.h>
>>>> @@ -802,7 +804,8 @@ static int __init gic_init_bases(void __iomem *dist_base,
>>>> set_handle_irq(gic_handle_irq);
>>>>
>>>> if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
>>>> - its_init(domain_token, &gic_data.rdists, gic_data.domain);
>>>> + its_init(irq_domain_token_to_of_node(domain_token),
>>>> + &gic_data.rdists, gic_data.domain);
>>>
>>> This doesn't make much sense. The first parameter to its_init is indeed
>>> supposed to be an of_node, but what is the point of calling its_init if
>>> you *know* you don't have the necessary topological information to parse
>>> the firmware tables?
>>>
>>> I don't see *any* code that is going to parse the ITS table in this
>>> series, so please don't call its_init passing a NULL pointer to it. This
>>> is just gross.
>>
>> OK, the ITS ACPI code is in later patch which combined with IORT. How
>> about moving it to the GIC of init code temporary?
>
> Just don't call its_init if irq_domain_token_to_of_node(domain_token) is
> NULL. But don't call it with a NULL parameter.
OK.
[...]
>>>> +}
>>>> +IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_GIC_VERSION_V3, gic_acpi_init);
>>>> +IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_GIC_VERSION_V4, gic_acpi_init);
>>>
>>> As mentioned before, this doesn't work.
>>
>> hmm, I think we need more discussion for this one, but we need to match
>> V4 for GICv3 drivers, and everything will be the same in the dirver
>> as I said before.
>
> And as I said before, you don't need to distinguish v3 from v4 in the
> ACPI code. Matching GICv3 is enough.
OK, how about the following code when parsing the GIC version?
/*
* GICv3 driver can find out it's V3 or V4 itself, just set the
* gic_version to V3 to match the driver if firmware presented V4.
*/
if (gic_version == ACPI_MADT_GIC_VERSION_V4)
gic_version = ACPI_MADT_GIC_VERSION_V3;
Thanks
Hanjun
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| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-07-29 12:20 +0200 |
| Subject | [PATCH v4 05/10] irqchip / GICv3: remove the useless comparision of device node in xlate |
| Message-ID | <pRwCS-59z-21@gated-at.bofh.it> |
| In reply to | #1195003 |
In gic_irq_domain_xlate(), we match the domain's device node to the
controller and it turns out pretty useless, because we're always
registering the GIC domain with its device_node on DT, this is really
guaranteed to match.
Since we unify the way of matching irqdomain in DT and ACPI, this is
also a blocker of making this function usable in the context
of ACPI, so just remove it.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/irqchip/irq-gic-v3.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 19a65de..c0b96c6 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -706,8 +706,6 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
{
- if (irq_domain_get_of_node(d) != controller)
- return -EINVAL;
if (intsize < 3)
return -EINVAL;
--
1.9.1
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| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-07-29 12:20 +0200 |
| Subject | [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures |
| Message-ID | <pRwCS-59z-25@gated-at.bofh.it> |
| In reply to | #1195003 |
On systems supporting GICv3 and above, in MADT GICC structures, the
field of GICR Base Address holds the 64-bit physical address of the
associated Redistributor if the GIC Redistributors are not in the
always-on power domain, so instead of init GICR regions via GIC
redistributor structure(s), init it with GICR base address in GICC
structures in that case.
As GICR base in MADT GICC is another way to indicate the GIC version
is 3 or 4, add its support to find out the GIC versions.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/irqchip/irq-gic-acpi.c | 35 ++++++-
drivers/irqchip/irq-gic-v3.c | 197 +++++++++++++++++++++++++++++++----
include/linux/irqchip/arm-gic-acpi.h | 2 +
3 files changed, 215 insertions(+), 19 deletions(-)
diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c
index 95454e3..3e5c8f4 100644
--- a/drivers/irqchip/irq-gic-acpi.c
+++ b/drivers/irqchip/irq-gic-acpi.c
@@ -21,6 +21,11 @@ static u8 gic_version __initdata = ACPI_MADT_GIC_VERSION_NONE;
static phys_addr_t dist_phy_base __initdata;
+u8 __init acpi_gic_version(void)
+{
+ return gic_version;
+}
+
static int __init
acpi_gic_parse_distributor(struct acpi_subtable_header *header,
const unsigned long end)
@@ -38,6 +43,27 @@ acpi_gic_parse_distributor(struct acpi_subtable_header *header,
}
static int __init
+gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_interrupt *gicc;
+
+ gicc = (struct acpi_madt_generic_interrupt *)header;
+
+ if (BAD_MADT_GICC_ENTRY(gicc, end))
+ return -EINVAL;
+
+ /*
+ * If GICC is enabled but has no valid gicr base address, then it
+ * means GICR base is not presented via GICC
+ */
+ if ((gicc->flags & ACPI_MADT_ENABLED) && !gicc->gicr_base_address)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int __init
match_gic_redist(struct acpi_subtable_header *header, const unsigned long end)
{
return 0;
@@ -51,7 +77,14 @@ static bool __init acpi_gic_redist_is_present(void)
count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
match_gic_redist, 0);
- /* that's true if we have at least one GIC redistributor entry */
+ /* has at least one GIC redistributor entry */
+ if (count > 0)
+ return true;
+
+ /* else try to find GICR base in GICC entries */
+ count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
+ gic_acpi_parse_madt_gicc, 0);
+
return count > 0;
}
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index ebc5604..b72ccbb 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -389,9 +389,8 @@ static void __init gic_dist_init(void)
writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
}
-static int gic_populate_rdist(void)
+static int gic_populate_rdist_with_regions(u64 mpidr)
{
- u64 mpidr = cpu_logical_map(smp_processor_id());
u64 typer;
u32 aff;
int i;
@@ -439,6 +438,34 @@ static int gic_populate_rdist(void)
} while (!(typer & GICR_TYPER_LAST));
}
+ return -ENODEV;
+}
+
+#ifdef CONFIG_ACPI
+/*
+ * Populate redist when GIC redistributor address is presented in ACPI
+ * MADT GICC entries
+ */
+static int gic_populate_rdist_with_gicr_base(u64 mpidr);
+#else
+static inline int gic_populate_rdist_with_gicr_base(u64 mpidr)
+{
+ return -ENODEV;
+}
+#endif
+
+static int gic_populate_rdist(void)
+{
+ u64 mpidr = cpu_logical_map(smp_processor_id());
+
+ if (gic_data.nr_redist_regions) {
+ if (!gic_populate_rdist_with_regions(mpidr))
+ return 0;
+ } else {
+ if (!gic_populate_rdist_with_gicr_base(mpidr))
+ return 0;
+ }
+
/* We couldn't even deal with ourselves... */
WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
smp_processor_id(), (unsigned long long)mpidr);
@@ -900,6 +927,16 @@ IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
#endif
#ifdef CONFIG_ACPI
+
+struct acpi_gicc_redist {
+ struct list_head list;
+ u64 mpidr;
+ phys_addr_t phys_base;
+ void __iomem *redist_base;
+};
+
+static LIST_HEAD(redist_list);
+
static struct redist_region *redist_regs __initdata;
static u32 nr_redist_regions __initdata;
static phys_addr_t dist_phys_base __initdata;
@@ -932,6 +969,17 @@ gic_acpi_register_redist(u64 phys_base, u64 size)
return 0;
}
+static void __init
+gic_acpi_release_redist_regions(void)
+{
+ int i;
+
+ for (i = 0; i < nr_redist_regions; i++)
+ if (redist_regs[i].redist_base)
+ iounmap(redist_regs[i].redist_base);
+ kfree(redist_regs);
+}
+
static int __init
gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
const unsigned long end)
@@ -989,9 +1037,130 @@ static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
}
static int __init
+gic_acpi_add_gicc_redist(phys_addr_t phys_base, u64 mpidr)
+{
+ struct acpi_gicc_redist *redist;
+
+ redist = kzalloc(sizeof(*redist), GFP_KERNEL);
+ if (!redist)
+ return -ENOMEM;
+
+ redist->mpidr = mpidr;
+ redist->phys_base = phys_base;
+
+ if (acpi_gic_version() == ACPI_MADT_GIC_VERSION_V3)
+ /* RD_base + SGI_base */
+ redist->redist_base = ioremap(phys_base, 2 * SZ_64K);
+ else
+ /*
+ * RD_base + SGI_base + VLPI_base,
+ * we don't map reserved page as it's buggy to access it
+ */
+ redist->redist_base = ioremap(phys_base, 3 * SZ_64K);
+
+ if (!redist->redist_base) {
+ kfree(redist);
+ return -ENOMEM;
+ }
+
+ list_add(&redist->list, &redist_list);
+ return 0;
+}
+
+static void __init
+gic_acpi_release_gicc_redist(void)
+{
+ struct acpi_gicc_redist *redist, *t;
+
+ list_for_each_entry_safe(redist, t, &redist_list, list) {
+ list_del(&redist->list);
+ iounmap(redist->redist_base);
+ kfree(redist);
+ }
+}
+
+static int __init
+gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_interrupt *gicc;
+
+ gicc = (struct acpi_madt_generic_interrupt *)header;
+
+ if (BAD_MADT_GICC_ENTRY(gicc, end))
+ return -EINVAL;
+
+ /*
+ * just quietly ingore the disabled CPU(s) and continue
+ * to find the enabled one(s), if we return error here,
+ * the scanning will be stopped.
+ */
+ if (!(gicc->flags & ACPI_MADT_ENABLED))
+ return 0;
+
+ return gic_acpi_add_gicc_redist(gicc->gicr_base_address,
+ gicc->arm_mpidr);
+}
+
+static int gic_populate_rdist_with_gicr_base(u64 mpidr)
+{
+ struct acpi_gicc_redist *redist;
+ void __iomem *ptr;
+ u32 reg;
+
+ list_for_each_entry(redist, &redist_list, list) {
+ if (redist->mpidr != mpidr)
+ continue;
+
+ ptr = redist->redist_base;
+ reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
+ if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
+ pr_warn("No redistributor present @%p\n", ptr);
+ return -ENODEV;
+ }
+
+ gic_data_rdist_rd_base() = ptr;
+ gic_data_rdist()->phys_base = redist->phys_base;
+ pr_info("CPU%d: found redistributor %llx phys base:%pa\n",
+ smp_processor_id(),
+ (unsigned long long)mpidr,
+ &gic_data_rdist()->phys_base);
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+static int __init collect_gicr_base(struct acpi_table_header *table)
+{
+ int count;
+
+ /* Collect redistributor base addresses in GICR entries */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_redist, table,
+ ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
+ if (count > 0)
+ return 0;
+
+ pr_info("No valid GICR entries exist, try GICC entries\n");
+
+ /* Collect redistributor base addresses in GICC entries */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_gicc, table,
+ ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
+ if (count > 0 && !list_empty(&redist_list))
+ return 0;
+
+ pr_info("No valid GICC entries exist for GICR base\n");
+ return -ENODEV;
+}
+
+static int __init
gic_acpi_init(struct acpi_table_header *table)
{
- int count, i, err = 0;
+ int count, err = 0;
void __iomem *dist_base;
/* Get distributor base address */
@@ -1020,30 +1189,22 @@ gic_acpi_init(struct acpi_table_header *table)
}
/* Collect redistributor base addresses */
- count = acpi_parse_entries(ACPI_SIG_MADT,
- sizeof(struct acpi_table_madt),
- gic_acpi_parse_madt_redist, table,
- ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
- if (count <= 0) {
- pr_info("No valid GICR entries exist\n");
- err = -EINVAL;
- goto out_redist_unmap;
- }
+ if (collect_gicr_base(table))
+ goto out_release_redist;
err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
(void *)ACPI_IRQ_MODEL_GIC);
if (err)
- goto out_redist_unmap;
+ goto out_release_redist;
acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
gic_acpi_gsi_desc_populate);
return 0;
-out_redist_unmap:
- for (i = 0; i < nr_redist_regions; i++)
- if (redist_regs[i].redist_base)
- iounmap(redist_regs[i].redist_base);
- kfree(redist_regs);
+out_release_redist:
+ gic_acpi_release_redist_regions();
+ if (!list_empty(&redist_list))
+ gic_acpi_release_gicc_redist();
out_dist_unmap:
iounmap(dist_base);
return err;
diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
index 56cd82c..0d43f515 100644
--- a/include/linux/irqchip/arm-gic-acpi.h
+++ b/include/linux/irqchip/arm-gic-acpi.h
@@ -21,5 +21,7 @@
#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
+u8 acpi_gic_version(void);
+
#endif /* CONFIG_ACPI */
#endif /* ARM_GIC_ACPI_H_ */
--
1.9.1
--
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[toc] | [prev] | [next] | [standalone]
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-04 15:40 +0200 |
| Subject | Re: [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures |
| Message-ID | <pTKBH-3xf-3@gated-at.bofh.it> |
| In reply to | #1195021 |
On 29/07/15 11:08, Hanjun Guo wrote:
> On systems supporting GICv3 and above, in MADT GICC structures, the
> field of GICR Base Address holds the 64-bit physical address of the
> associated Redistributor if the GIC Redistributors are not in the
> always-on power domain, so instead of init GICR regions via GIC
> redistributor structure(s), init it with GICR base address in GICC
> structures in that case.
>
> As GICR base in MADT GICC is another way to indicate the GIC version
> is 3 or 4, add its support to find out the GIC versions.
>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> ---
> drivers/irqchip/irq-gic-acpi.c | 35 ++++++-
> drivers/irqchip/irq-gic-v3.c | 197 +++++++++++++++++++++++++++++++----
> include/linux/irqchip/arm-gic-acpi.h | 2 +
> 3 files changed, 215 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c
> index 95454e3..3e5c8f4 100644
> --- a/drivers/irqchip/irq-gic-acpi.c
> +++ b/drivers/irqchip/irq-gic-acpi.c
> @@ -21,6 +21,11 @@ static u8 gic_version __initdata = ACPI_MADT_GIC_VERSION_NONE;
>
> static phys_addr_t dist_phy_base __initdata;
>
> +u8 __init acpi_gic_version(void)
> +{
> + return gic_version;
> +}
> +
> static int __init
> acpi_gic_parse_distributor(struct acpi_subtable_header *header,
> const unsigned long end)
> @@ -38,6 +43,27 @@ acpi_gic_parse_distributor(struct acpi_subtable_header *header,
> }
>
> static int __init
> +gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_generic_interrupt *gicc;
> +
> + gicc = (struct acpi_madt_generic_interrupt *)header;
> +
> + if (BAD_MADT_GICC_ENTRY(gicc, end))
> + return -EINVAL;
> +
> + /*
> + * If GICC is enabled but has no valid gicr base address, then it
> + * means GICR base is not presented via GICC
> + */
> + if ((gicc->flags & ACPI_MADT_ENABLED) && !gicc->gicr_base_address)
> + return -ENODEV;
> +
> + return 0;
> +}
> +
> +static int __init
> match_gic_redist(struct acpi_subtable_header *header, const unsigned long end)
> {
> return 0;
> @@ -51,7 +77,14 @@ static bool __init acpi_gic_redist_is_present(void)
> count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
> match_gic_redist, 0);
>
> - /* that's true if we have at least one GIC redistributor entry */
> + /* has at least one GIC redistributor entry */
> + if (count > 0)
> + return true;
> +
> + /* else try to find GICR base in GICC entries */
> + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
> + gic_acpi_parse_madt_gicc, 0);
> +
> return count > 0;
> }
>
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index ebc5604..b72ccbb 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -389,9 +389,8 @@ static void __init gic_dist_init(void)
> writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
> }
>
> -static int gic_populate_rdist(void)
> +static int gic_populate_rdist_with_regions(u64 mpidr)
> {
> - u64 mpidr = cpu_logical_map(smp_processor_id());
> u64 typer;
> u32 aff;
> int i;
> @@ -439,6 +438,34 @@ static int gic_populate_rdist(void)
> } while (!(typer & GICR_TYPER_LAST));
> }
>
> + return -ENODEV;
> +}
> +
> +#ifdef CONFIG_ACPI
> +/*
> + * Populate redist when GIC redistributor address is presented in ACPI
> + * MADT GICC entries
> + */
> +static int gic_populate_rdist_with_gicr_base(u64 mpidr);
> +#else
> +static inline int gic_populate_rdist_with_gicr_base(u64 mpidr)
> +{
> + return -ENODEV;
> +}
> +#endif
> +
> +static int gic_populate_rdist(void)
> +{
> + u64 mpidr = cpu_logical_map(smp_processor_id());
> +
> + if (gic_data.nr_redist_regions) {
> + if (!gic_populate_rdist_with_regions(mpidr))
> + return 0;
> + } else {
> + if (!gic_populate_rdist_with_gicr_base(mpidr))
> + return 0;
> + }
> +
> /* We couldn't even deal with ourselves... */
> WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
> smp_processor_id(), (unsigned long long)mpidr);
> @@ -900,6 +927,16 @@ IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
> #endif
>
> #ifdef CONFIG_ACPI
> +
> +struct acpi_gicc_redist {
> + struct list_head list;
> + u64 mpidr;
> + phys_addr_t phys_base;
> + void __iomem *redist_base;
> +};
> +
> +static LIST_HEAD(redist_list);
> +
> static struct redist_region *redist_regs __initdata;
> static u32 nr_redist_regions __initdata;
> static phys_addr_t dist_phys_base __initdata;
> @@ -932,6 +969,17 @@ gic_acpi_register_redist(u64 phys_base, u64 size)
> return 0;
> }
>
> +static void __init
> +gic_acpi_release_redist_regions(void)
> +{
> + int i;
> +
> + for (i = 0; i < nr_redist_regions; i++)
> + if (redist_regs[i].redist_base)
> + iounmap(redist_regs[i].redist_base);
> + kfree(redist_regs);
> +}
> +
> static int __init
> gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
> const unsigned long end)
> @@ -989,9 +1037,130 @@ static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
> }
>
> static int __init
> +gic_acpi_add_gicc_redist(phys_addr_t phys_base, u64 mpidr)
> +{
> + struct acpi_gicc_redist *redist;
> +
> + redist = kzalloc(sizeof(*redist), GFP_KERNEL);
> + if (!redist)
> + return -ENOMEM;
> +
> + redist->mpidr = mpidr;
> + redist->phys_base = phys_base;
> +
> + if (acpi_gic_version() == ACPI_MADT_GIC_VERSION_V3)
> + /* RD_base + SGI_base */
> + redist->redist_base = ioremap(phys_base, 2 * SZ_64K);
> + else
> + /*
> + * RD_base + SGI_base + VLPI_base,
> + * we don't map reserved page as it's buggy to access it
> + */
> + redist->redist_base = ioremap(phys_base, 3 * SZ_64K);
> +
> + if (!redist->redist_base) {
> + kfree(redist);
> + return -ENOMEM;
> + }
> +
> + list_add(&redist->list, &redist_list);
> + return 0;
> +}
> +
> +static void __init
> +gic_acpi_release_gicc_redist(void)
> +{
> + struct acpi_gicc_redist *redist, *t;
> +
> + list_for_each_entry_safe(redist, t, &redist_list, list) {
> + list_del(&redist->list);
> + iounmap(redist->redist_base);
> + kfree(redist);
> + }
> +}
> +
> +static int __init
> +gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_generic_interrupt *gicc;
> +
> + gicc = (struct acpi_madt_generic_interrupt *)header;
> +
> + if (BAD_MADT_GICC_ENTRY(gicc, end))
> + return -EINVAL;
> +
> + /*
> + * just quietly ingore the disabled CPU(s) and continue
> + * to find the enabled one(s), if we return error here,
> + * the scanning will be stopped.
> + */
> + if (!(gicc->flags & ACPI_MADT_ENABLED))
> + return 0;
> +
> + return gic_acpi_add_gicc_redist(gicc->gicr_base_address,
> + gicc->arm_mpidr);
> +}
> +
> +static int gic_populate_rdist_with_gicr_base(u64 mpidr)
> +{
> + struct acpi_gicc_redist *redist;
> + void __iomem *ptr;
> + u32 reg;
> +
> + list_for_each_entry(redist, &redist_list, list) {
> + if (redist->mpidr != mpidr)
> + continue;
> +
> + ptr = redist->redist_base;
> + reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
> + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
> + pr_warn("No redistributor present @%p\n", ptr);
> + return -ENODEV;
> + }
> +
> + gic_data_rdist_rd_base() = ptr;
> + gic_data_rdist()->phys_base = redist->phys_base;
> + pr_info("CPU%d: found redistributor %llx phys base:%pa\n",
> + smp_processor_id(),
> + (unsigned long long)mpidr,
> + &gic_data_rdist()->phys_base);
> + return 0;
> + }
> +
> + return -ENODEV;
> +}
> +
> +static int __init collect_gicr_base(struct acpi_table_header *table)
> +{
> + int count;
> +
> + /* Collect redistributor base addresses in GICR entries */
> + count = acpi_parse_entries(ACPI_SIG_MADT,
> + sizeof(struct acpi_table_madt),
> + gic_acpi_parse_madt_redist, table,
> + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
> + if (count > 0)
> + return 0;
> +
> + pr_info("No valid GICR entries exist, try GICC entries\n");
> +
> + /* Collect redistributor base addresses in GICC entries */
> + count = acpi_parse_entries(ACPI_SIG_MADT,
> + sizeof(struct acpi_table_madt),
> + gic_acpi_parse_madt_gicc, table,
> + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
> + if (count > 0 && !list_empty(&redist_list))
> + return 0;
> +
> + pr_info("No valid GICC entries exist for GICR base\n");
> + return -ENODEV;
> +}
> +
> +static int __init
> gic_acpi_init(struct acpi_table_header *table)
> {
> - int count, i, err = 0;
> + int count, err = 0;
> void __iomem *dist_base;
>
> /* Get distributor base address */
> @@ -1020,30 +1189,22 @@ gic_acpi_init(struct acpi_table_header *table)
> }
>
> /* Collect redistributor base addresses */
> - count = acpi_parse_entries(ACPI_SIG_MADT,
> - sizeof(struct acpi_table_madt),
> - gic_acpi_parse_madt_redist, table,
> - ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
> - if (count <= 0) {
> - pr_info("No valid GICR entries exist\n");
> - err = -EINVAL;
> - goto out_redist_unmap;
> - }
> + if (collect_gicr_base(table))
> + goto out_release_redist;
>
> err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
> (void *)ACPI_IRQ_MODEL_GIC);
> if (err)
> - goto out_redist_unmap;
> + goto out_release_redist;
>
> acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
> gic_acpi_gsi_desc_populate);
> return 0;
>
> -out_redist_unmap:
> - for (i = 0; i < nr_redist_regions; i++)
> - if (redist_regs[i].redist_base)
> - iounmap(redist_regs[i].redist_base);
> - kfree(redist_regs);
> +out_release_redist:
> + gic_acpi_release_redist_regions();
> + if (!list_empty(&redist_list))
> + gic_acpi_release_gicc_redist();
> out_dist_unmap:
> iounmap(dist_base);
> return err;
> diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
> index 56cd82c..0d43f515 100644
> --- a/include/linux/irqchip/arm-gic-acpi.h
> +++ b/include/linux/irqchip/arm-gic-acpi.h
> @@ -21,5 +21,7 @@
> #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
> #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
>
> +u8 acpi_gic_version(void);
> +
> #endif /* CONFIG_ACPI */
> #endif /* ARM_GIC_ACPI_H_ */
> --
> 1.9.1
>
This looks absolutely horrid. Why don't you simply populate one region
per redistributor, add a flag to struct redist_region so we know not to
check for GICR_TYPER_LAST but to move on to the next region instead?
We already have all the flexibility you require, please don't invent
stuff that is already there.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-08-05 16:20 +0200 |
| Subject | Re: [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures |
| Message-ID | <pU7HY-3KF-11@gated-at.bofh.it> |
| In reply to | #1199840 |
On 08/04/2015 09:37 PM, Marc Zyngier wrote:
> On 29/07/15 11:08, Hanjun Guo wrote:
>> On systems supporting GICv3 and above, in MADT GICC structures, the
>> field of GICR Base Address holds the 64-bit physical address of the
>> associated Redistributor if the GIC Redistributors are not in the
>> always-on power domain, so instead of init GICR regions via GIC
>> redistributor structure(s), init it with GICR base address in GICC
>> structures in that case.
>>
>> As GICR base in MADT GICC is another way to indicate the GIC version
>> is 3 or 4, add its support to find out the GIC versions.
>>
>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>> ---
>> drivers/irqchip/irq-gic-acpi.c | 35 ++++++-
>> drivers/irqchip/irq-gic-v3.c | 197 +++++++++++++++++++++++++++++++----
>> include/linux/irqchip/arm-gic-acpi.h | 2 +
>> 3 files changed, 215 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c
>> index 95454e3..3e5c8f4 100644
>> --- a/drivers/irqchip/irq-gic-acpi.c
>> +++ b/drivers/irqchip/irq-gic-acpi.c
>> @@ -21,6 +21,11 @@ static u8 gic_version __initdata = ACPI_MADT_GIC_VERSION_NONE;
>>
>> static phys_addr_t dist_phy_base __initdata;
>>
>> +u8 __init acpi_gic_version(void)
>> +{
>> + return gic_version;
>> +}
>> +
>> static int __init
>> acpi_gic_parse_distributor(struct acpi_subtable_header *header,
>> const unsigned long end)
>> @@ -38,6 +43,27 @@ acpi_gic_parse_distributor(struct acpi_subtable_header *header,
>> }
>>
>> static int __init
>> +gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_generic_interrupt *gicc;
>> +
>> + gicc = (struct acpi_madt_generic_interrupt *)header;
>> +
>> + if (BAD_MADT_GICC_ENTRY(gicc, end))
>> + return -EINVAL;
>> +
>> + /*
>> + * If GICC is enabled but has no valid gicr base address, then it
>> + * means GICR base is not presented via GICC
>> + */
>> + if ((gicc->flags & ACPI_MADT_ENABLED) && !gicc->gicr_base_address)
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>> +
>> +static int __init
>> match_gic_redist(struct acpi_subtable_header *header, const unsigned long end)
>> {
>> return 0;
>> @@ -51,7 +77,14 @@ static bool __init acpi_gic_redist_is_present(void)
>> count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
>> match_gic_redist, 0);
>>
>> - /* that's true if we have at least one GIC redistributor entry */
>> + /* has at least one GIC redistributor entry */
>> + if (count > 0)
>> + return true;
>> +
>> + /* else try to find GICR base in GICC entries */
>> + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
>> + gic_acpi_parse_madt_gicc, 0);
>> +
>> return count > 0;
>> }
>>
>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>> index ebc5604..b72ccbb 100644
>> --- a/drivers/irqchip/irq-gic-v3.c
>> +++ b/drivers/irqchip/irq-gic-v3.c
>> @@ -389,9 +389,8 @@ static void __init gic_dist_init(void)
>> writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
>> }
>>
>> -static int gic_populate_rdist(void)
>> +static int gic_populate_rdist_with_regions(u64 mpidr)
>> {
>> - u64 mpidr = cpu_logical_map(smp_processor_id());
>> u64 typer;
>> u32 aff;
>> int i;
>> @@ -439,6 +438,34 @@ static int gic_populate_rdist(void)
>> } while (!(typer & GICR_TYPER_LAST));
>> }
>>
>> + return -ENODEV;
>> +}
>> +
>> +#ifdef CONFIG_ACPI
>> +/*
>> + * Populate redist when GIC redistributor address is presented in ACPI
>> + * MADT GICC entries
>> + */
>> +static int gic_populate_rdist_with_gicr_base(u64 mpidr);
>> +#else
>> +static inline int gic_populate_rdist_with_gicr_base(u64 mpidr)
>> +{
>> + return -ENODEV;
>> +}
>> +#endif
>> +
>> +static int gic_populate_rdist(void)
>> +{
>> + u64 mpidr = cpu_logical_map(smp_processor_id());
>> +
>> + if (gic_data.nr_redist_regions) {
>> + if (!gic_populate_rdist_with_regions(mpidr))
>> + return 0;
>> + } else {
>> + if (!gic_populate_rdist_with_gicr_base(mpidr))
>> + return 0;
>> + }
>> +
>> /* We couldn't even deal with ourselves... */
>> WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
>> smp_processor_id(), (unsigned long long)mpidr);
>> @@ -900,6 +927,16 @@ IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
>> #endif
>>
>> #ifdef CONFIG_ACPI
>> +
>> +struct acpi_gicc_redist {
>> + struct list_head list;
>> + u64 mpidr;
>> + phys_addr_t phys_base;
>> + void __iomem *redist_base;
>> +};
>> +
>> +static LIST_HEAD(redist_list);
>> +
>> static struct redist_region *redist_regs __initdata;
>> static u32 nr_redist_regions __initdata;
>> static phys_addr_t dist_phys_base __initdata;
>> @@ -932,6 +969,17 @@ gic_acpi_register_redist(u64 phys_base, u64 size)
>> return 0;
>> }
>>
>> +static void __init
>> +gic_acpi_release_redist_regions(void)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < nr_redist_regions; i++)
>> + if (redist_regs[i].redist_base)
>> + iounmap(redist_regs[i].redist_base);
>> + kfree(redist_regs);
>> +}
>> +
>> static int __init
>> gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
>> const unsigned long end)
>> @@ -989,9 +1037,130 @@ static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
>> }
>>
>> static int __init
>> +gic_acpi_add_gicc_redist(phys_addr_t phys_base, u64 mpidr)
>> +{
>> + struct acpi_gicc_redist *redist;
>> +
>> + redist = kzalloc(sizeof(*redist), GFP_KERNEL);
>> + if (!redist)
>> + return -ENOMEM;
>> +
>> + redist->mpidr = mpidr;
>> + redist->phys_base = phys_base;
>> +
>> + if (acpi_gic_version() == ACPI_MADT_GIC_VERSION_V3)
>> + /* RD_base + SGI_base */
>> + redist->redist_base = ioremap(phys_base, 2 * SZ_64K);
>> + else
>> + /*
>> + * RD_base + SGI_base + VLPI_base,
>> + * we don't map reserved page as it's buggy to access it
>> + */
>> + redist->redist_base = ioremap(phys_base, 3 * SZ_64K);
>> +
>> + if (!redist->redist_base) {
>> + kfree(redist);
>> + return -ENOMEM;
>> + }
>> +
>> + list_add(&redist->list, &redist_list);
>> + return 0;
>> +}
>> +
>> +static void __init
>> +gic_acpi_release_gicc_redist(void)
>> +{
>> + struct acpi_gicc_redist *redist, *t;
>> +
>> + list_for_each_entry_safe(redist, t, &redist_list, list) {
>> + list_del(&redist->list);
>> + iounmap(redist->redist_base);
>> + kfree(redist);
>> + }
>> +}
>> +
>> +static int __init
>> +gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
>> + const unsigned long end)
>> +{
>> + struct acpi_madt_generic_interrupt *gicc;
>> +
>> + gicc = (struct acpi_madt_generic_interrupt *)header;
>> +
>> + if (BAD_MADT_GICC_ENTRY(gicc, end))
>> + return -EINVAL;
>> +
>> + /*
>> + * just quietly ingore the disabled CPU(s) and continue
>> + * to find the enabled one(s), if we return error here,
>> + * the scanning will be stopped.
>> + */
>> + if (!(gicc->flags & ACPI_MADT_ENABLED))
>> + return 0;
>> +
>> + return gic_acpi_add_gicc_redist(gicc->gicr_base_address,
>> + gicc->arm_mpidr);
>> +}
>> +
>> +static int gic_populate_rdist_with_gicr_base(u64 mpidr)
>> +{
>> + struct acpi_gicc_redist *redist;
>> + void __iomem *ptr;
>> + u32 reg;
>> +
>> + list_for_each_entry(redist, &redist_list, list) {
>> + if (redist->mpidr != mpidr)
>> + continue;
>> +
>> + ptr = redist->redist_base;
>> + reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
>> + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
>> + pr_warn("No redistributor present @%p\n", ptr);
>> + return -ENODEV;
>> + }
>> +
>> + gic_data_rdist_rd_base() = ptr;
>> + gic_data_rdist()->phys_base = redist->phys_base;
>> + pr_info("CPU%d: found redistributor %llx phys base:%pa\n",
>> + smp_processor_id(),
>> + (unsigned long long)mpidr,
>> + &gic_data_rdist()->phys_base);
>> + return 0;
>> + }
>> +
>> + return -ENODEV;
>> +}
>> +
>> +static int __init collect_gicr_base(struct acpi_table_header *table)
>> +{
>> + int count;
>> +
>> + /* Collect redistributor base addresses in GICR entries */
>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>> + sizeof(struct acpi_table_madt),
>> + gic_acpi_parse_madt_redist, table,
>> + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
>> + if (count > 0)
>> + return 0;
>> +
>> + pr_info("No valid GICR entries exist, try GICC entries\n");
>> +
>> + /* Collect redistributor base addresses in GICC entries */
>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>> + sizeof(struct acpi_table_madt),
>> + gic_acpi_parse_madt_gicc, table,
>> + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
>> + if (count > 0 && !list_empty(&redist_list))
>> + return 0;
>> +
>> + pr_info("No valid GICC entries exist for GICR base\n");
>> + return -ENODEV;
>> +}
>> +
>> +static int __init
>> gic_acpi_init(struct acpi_table_header *table)
>> {
>> - int count, i, err = 0;
>> + int count, err = 0;
>> void __iomem *dist_base;
>>
>> /* Get distributor base address */
>> @@ -1020,30 +1189,22 @@ gic_acpi_init(struct acpi_table_header *table)
>> }
>>
>> /* Collect redistributor base addresses */
>> - count = acpi_parse_entries(ACPI_SIG_MADT,
>> - sizeof(struct acpi_table_madt),
>> - gic_acpi_parse_madt_redist, table,
>> - ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
>> - if (count <= 0) {
>> - pr_info("No valid GICR entries exist\n");
>> - err = -EINVAL;
>> - goto out_redist_unmap;
>> - }
>> + if (collect_gicr_base(table))
>> + goto out_release_redist;
>>
>> err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
>> (void *)ACPI_IRQ_MODEL_GIC);
>> if (err)
>> - goto out_redist_unmap;
>> + goto out_release_redist;
>>
>> acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
>> gic_acpi_gsi_desc_populate);
>> return 0;
>>
>> -out_redist_unmap:
>> - for (i = 0; i < nr_redist_regions; i++)
>> - if (redist_regs[i].redist_base)
>> - iounmap(redist_regs[i].redist_base);
>> - kfree(redist_regs);
>> +out_release_redist:
>> + gic_acpi_release_redist_regions();
>> + if (!list_empty(&redist_list))
>> + gic_acpi_release_gicc_redist();
>> out_dist_unmap:
>> iounmap(dist_base);
>> return err;
>> diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
>> index 56cd82c..0d43f515 100644
>> --- a/include/linux/irqchip/arm-gic-acpi.h
>> +++ b/include/linux/irqchip/arm-gic-acpi.h
>> @@ -21,5 +21,7 @@
>> #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
>> #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
>>
>> +u8 acpi_gic_version(void);
>> +
>> #endif /* CONFIG_ACPI */
>> #endif /* ARM_GIC_ACPI_H_ */
>> --
>> 1.9.1
>>
>
> This looks absolutely horrid. Why don't you simply populate one region
> per redistributor, add a flag to struct redist_region so we know not to
> check for GICR_TYPER_LAST but to move on to the next region instead?
There is no regions in GICC structures, and only have the GICR base
address for each CPU, I think we can't figure out which GICR bases
are belonging to a GICR region.
So do you mean populate each GICR base as a region, and use the
existing infrastructure ?
Thanks
Hanjun
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-06 18:50 +0200 |
| Subject | Re: [PATCH v4 07/10] irqchip / GICv3 / ACPI: Add GICR support via GICC structures |
| Message-ID | <pUwwF-6kc-1@gated-at.bofh.it> |
| In reply to | #1200817 |
On 05/08/15 15:11, Hanjun Guo wrote:
> On 08/04/2015 09:37 PM, Marc Zyngier wrote:
>> On 29/07/15 11:08, Hanjun Guo wrote:
>>> On systems supporting GICv3 and above, in MADT GICC structures, the
>>> field of GICR Base Address holds the 64-bit physical address of the
>>> associated Redistributor if the GIC Redistributors are not in the
>>> always-on power domain, so instead of init GICR regions via GIC
>>> redistributor structure(s), init it with GICR base address in GICC
>>> structures in that case.
>>>
>>> As GICR base in MADT GICC is another way to indicate the GIC version
>>> is 3 or 4, add its support to find out the GIC versions.
>>>
>>> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
>>> ---
>>> drivers/irqchip/irq-gic-acpi.c | 35 ++++++-
>>> drivers/irqchip/irq-gic-v3.c | 197 +++++++++++++++++++++++++++++++----
>>> include/linux/irqchip/arm-gic-acpi.h | 2 +
>>> 3 files changed, 215 insertions(+), 19 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-gic-acpi.c b/drivers/irqchip/irq-gic-acpi.c
>>> index 95454e3..3e5c8f4 100644
>>> --- a/drivers/irqchip/irq-gic-acpi.c
>>> +++ b/drivers/irqchip/irq-gic-acpi.c
>>> @@ -21,6 +21,11 @@ static u8 gic_version __initdata = ACPI_MADT_GIC_VERSION_NONE;
>>>
>>> static phys_addr_t dist_phy_base __initdata;
>>>
>>> +u8 __init acpi_gic_version(void)
>>> +{
>>> + return gic_version;
>>> +}
>>> +
>>> static int __init
>>> acpi_gic_parse_distributor(struct acpi_subtable_header *header,
>>> const unsigned long end)
>>> @@ -38,6 +43,27 @@ acpi_gic_parse_distributor(struct acpi_subtable_header *header,
>>> }
>>>
>>> static int __init
>>> +gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
>>> + const unsigned long end)
>>> +{
>>> + struct acpi_madt_generic_interrupt *gicc;
>>> +
>>> + gicc = (struct acpi_madt_generic_interrupt *)header;
>>> +
>>> + if (BAD_MADT_GICC_ENTRY(gicc, end))
>>> + return -EINVAL;
>>> +
>>> + /*
>>> + * If GICC is enabled but has no valid gicr base address, then it
>>> + * means GICR base is not presented via GICC
>>> + */
>>> + if ((gicc->flags & ACPI_MADT_ENABLED) && !gicc->gicr_base_address)
>>> + return -ENODEV;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int __init
>>> match_gic_redist(struct acpi_subtable_header *header, const unsigned long end)
>>> {
>>> return 0;
>>> @@ -51,7 +77,14 @@ static bool __init acpi_gic_redist_is_present(void)
>>> count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
>>> match_gic_redist, 0);
>>>
>>> - /* that's true if we have at least one GIC redistributor entry */
>>> + /* has at least one GIC redistributor entry */
>>> + if (count > 0)
>>> + return true;
>>> +
>>> + /* else try to find GICR base in GICC entries */
>>> + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
>>> + gic_acpi_parse_madt_gicc, 0);
>>> +
>>> return count > 0;
>>> }
>>>
>>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>>> index ebc5604..b72ccbb 100644
>>> --- a/drivers/irqchip/irq-gic-v3.c
>>> +++ b/drivers/irqchip/irq-gic-v3.c
>>> @@ -389,9 +389,8 @@ static void __init gic_dist_init(void)
>>> writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
>>> }
>>>
>>> -static int gic_populate_rdist(void)
>>> +static int gic_populate_rdist_with_regions(u64 mpidr)
>>> {
>>> - u64 mpidr = cpu_logical_map(smp_processor_id());
>>> u64 typer;
>>> u32 aff;
>>> int i;
>>> @@ -439,6 +438,34 @@ static int gic_populate_rdist(void)
>>> } while (!(typer & GICR_TYPER_LAST));
>>> }
>>>
>>> + return -ENODEV;
>>> +}
>>> +
>>> +#ifdef CONFIG_ACPI
>>> +/*
>>> + * Populate redist when GIC redistributor address is presented in ACPI
>>> + * MADT GICC entries
>>> + */
>>> +static int gic_populate_rdist_with_gicr_base(u64 mpidr);
>>> +#else
>>> +static inline int gic_populate_rdist_with_gicr_base(u64 mpidr)
>>> +{
>>> + return -ENODEV;
>>> +}
>>> +#endif
>>> +
>>> +static int gic_populate_rdist(void)
>>> +{
>>> + u64 mpidr = cpu_logical_map(smp_processor_id());
>>> +
>>> + if (gic_data.nr_redist_regions) {
>>> + if (!gic_populate_rdist_with_regions(mpidr))
>>> + return 0;
>>> + } else {
>>> + if (!gic_populate_rdist_with_gicr_base(mpidr))
>>> + return 0;
>>> + }
>>> +
>>> /* We couldn't even deal with ourselves... */
>>> WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
>>> smp_processor_id(), (unsigned long long)mpidr);
>>> @@ -900,6 +927,16 @@ IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
>>> #endif
>>>
>>> #ifdef CONFIG_ACPI
>>> +
>>> +struct acpi_gicc_redist {
>>> + struct list_head list;
>>> + u64 mpidr;
>>> + phys_addr_t phys_base;
>>> + void __iomem *redist_base;
>>> +};
>>> +
>>> +static LIST_HEAD(redist_list);
>>> +
>>> static struct redist_region *redist_regs __initdata;
>>> static u32 nr_redist_regions __initdata;
>>> static phys_addr_t dist_phys_base __initdata;
>>> @@ -932,6 +969,17 @@ gic_acpi_register_redist(u64 phys_base, u64 size)
>>> return 0;
>>> }
>>>
>>> +static void __init
>>> +gic_acpi_release_redist_regions(void)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0; i < nr_redist_regions; i++)
>>> + if (redist_regs[i].redist_base)
>>> + iounmap(redist_regs[i].redist_base);
>>> + kfree(redist_regs);
>>> +}
>>> +
>>> static int __init
>>> gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
>>> const unsigned long end)
>>> @@ -989,9 +1037,130 @@ static int gic_acpi_gsi_desc_populate(struct acpi_gsi_descriptor *data,
>>> }
>>>
>>> static int __init
>>> +gic_acpi_add_gicc_redist(phys_addr_t phys_base, u64 mpidr)
>>> +{
>>> + struct acpi_gicc_redist *redist;
>>> +
>>> + redist = kzalloc(sizeof(*redist), GFP_KERNEL);
>>> + if (!redist)
>>> + return -ENOMEM;
>>> +
>>> + redist->mpidr = mpidr;
>>> + redist->phys_base = phys_base;
>>> +
>>> + if (acpi_gic_version() == ACPI_MADT_GIC_VERSION_V3)
>>> + /* RD_base + SGI_base */
>>> + redist->redist_base = ioremap(phys_base, 2 * SZ_64K);
>>> + else
>>> + /*
>>> + * RD_base + SGI_base + VLPI_base,
>>> + * we don't map reserved page as it's buggy to access it
>>> + */
>>> + redist->redist_base = ioremap(phys_base, 3 * SZ_64K);
>>> +
>>> + if (!redist->redist_base) {
>>> + kfree(redist);
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + list_add(&redist->list, &redist_list);
>>> + return 0;
>>> +}
>>> +
>>> +static void __init
>>> +gic_acpi_release_gicc_redist(void)
>>> +{
>>> + struct acpi_gicc_redist *redist, *t;
>>> +
>>> + list_for_each_entry_safe(redist, t, &redist_list, list) {
>>> + list_del(&redist->list);
>>> + iounmap(redist->redist_base);
>>> + kfree(redist);
>>> + }
>>> +}
>>> +
>>> +static int __init
>>> +gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
>>> + const unsigned long end)
>>> +{
>>> + struct acpi_madt_generic_interrupt *gicc;
>>> +
>>> + gicc = (struct acpi_madt_generic_interrupt *)header;
>>> +
>>> + if (BAD_MADT_GICC_ENTRY(gicc, end))
>>> + return -EINVAL;
>>> +
>>> + /*
>>> + * just quietly ingore the disabled CPU(s) and continue
>>> + * to find the enabled one(s), if we return error here,
>>> + * the scanning will be stopped.
>>> + */
>>> + if (!(gicc->flags & ACPI_MADT_ENABLED))
>>> + return 0;
>>> +
>>> + return gic_acpi_add_gicc_redist(gicc->gicr_base_address,
>>> + gicc->arm_mpidr);
>>> +}
>>> +
>>> +static int gic_populate_rdist_with_gicr_base(u64 mpidr)
>>> +{
>>> + struct acpi_gicc_redist *redist;
>>> + void __iomem *ptr;
>>> + u32 reg;
>>> +
>>> + list_for_each_entry(redist, &redist_list, list) {
>>> + if (redist->mpidr != mpidr)
>>> + continue;
>>> +
>>> + ptr = redist->redist_base;
>>> + reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
>>> + if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
>>> + pr_warn("No redistributor present @%p\n", ptr);
>>> + return -ENODEV;
>>> + }
>>> +
>>> + gic_data_rdist_rd_base() = ptr;
>>> + gic_data_rdist()->phys_base = redist->phys_base;
>>> + pr_info("CPU%d: found redistributor %llx phys base:%pa\n",
>>> + smp_processor_id(),
>>> + (unsigned long long)mpidr,
>>> + &gic_data_rdist()->phys_base);
>>> + return 0;
>>> + }
>>> +
>>> + return -ENODEV;
>>> +}
>>> +
>>> +static int __init collect_gicr_base(struct acpi_table_header *table)
>>> +{
>>> + int count;
>>> +
>>> + /* Collect redistributor base addresses in GICR entries */
>>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>>> + sizeof(struct acpi_table_madt),
>>> + gic_acpi_parse_madt_redist, table,
>>> + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
>>> + if (count > 0)
>>> + return 0;
>>> +
>>> + pr_info("No valid GICR entries exist, try GICC entries\n");
>>> +
>>> + /* Collect redistributor base addresses in GICC entries */
>>> + count = acpi_parse_entries(ACPI_SIG_MADT,
>>> + sizeof(struct acpi_table_madt),
>>> + gic_acpi_parse_madt_gicc, table,
>>> + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
>>> + if (count > 0 && !list_empty(&redist_list))
>>> + return 0;
>>> +
>>> + pr_info("No valid GICC entries exist for GICR base\n");
>>> + return -ENODEV;
>>> +}
>>> +
>>> +static int __init
>>> gic_acpi_init(struct acpi_table_header *table)
>>> {
>>> - int count, i, err = 0;
>>> + int count, err = 0;
>>> void __iomem *dist_base;
>>>
>>> /* Get distributor base address */
>>> @@ -1020,30 +1189,22 @@ gic_acpi_init(struct acpi_table_header *table)
>>> }
>>>
>>> /* Collect redistributor base addresses */
>>> - count = acpi_parse_entries(ACPI_SIG_MADT,
>>> - sizeof(struct acpi_table_madt),
>>> - gic_acpi_parse_madt_redist, table,
>>> - ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
>>> - if (count <= 0) {
>>> - pr_info("No valid GICR entries exist\n");
>>> - err = -EINVAL;
>>> - goto out_redist_unmap;
>>> - }
>>> + if (collect_gicr_base(table))
>>> + goto out_release_redist;
>>>
>>> err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0,
>>> (void *)ACPI_IRQ_MODEL_GIC);
>>> if (err)
>>> - goto out_redist_unmap;
>>> + goto out_release_redist;
>>>
>>> acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_GIC,
>>> gic_acpi_gsi_desc_populate);
>>> return 0;
>>>
>>> -out_redist_unmap:
>>> - for (i = 0; i < nr_redist_regions; i++)
>>> - if (redist_regs[i].redist_base)
>>> - iounmap(redist_regs[i].redist_base);
>>> - kfree(redist_regs);
>>> +out_release_redist:
>>> + gic_acpi_release_redist_regions();
>>> + if (!list_empty(&redist_list))
>>> + gic_acpi_release_gicc_redist();
>>> out_dist_unmap:
>>> iounmap(dist_base);
>>> return err;
>>> diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
>>> index 56cd82c..0d43f515 100644
>>> --- a/include/linux/irqchip/arm-gic-acpi.h
>>> +++ b/include/linux/irqchip/arm-gic-acpi.h
>>> @@ -21,5 +21,7 @@
>>> #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
>>> #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
>>>
>>> +u8 acpi_gic_version(void);
>>> +
>>> #endif /* CONFIG_ACPI */
>>> #endif /* ARM_GIC_ACPI_H_ */
>>> --
>>> 1.9.1
>>>
>>
>> This looks absolutely horrid. Why don't you simply populate one region
>> per redistributor, add a flag to struct redist_region so we know not to
>> check for GICR_TYPER_LAST but to move on to the next region instead?
>
> There is no regions in GICC structures, and only have the GICR base
> address for each CPU, I think we can't figure out which GICR bases
> are belonging to a GICR region.
>
> So do you mean populate each GICR base as a region, and use the
> existing infrastructure ?
This is exactly what I wrote.
Thanks,
M.
--
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| From | Hanjun Guo <hanjun.guo@linaro.org> |
|---|---|
| Date | 2015-07-29 12:20 +0200 |
| Subject | [PATCH v4 04/10] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver |
| Message-ID | <pRwCT-59z-29@gated-at.bofh.it> |
| In reply to | #1195003 |
From: Tomasz Nowicki <tomasz.nowicki@linaro.org>
Isolate hardware abstraction (FDT) code to gic_of_init().
Rest of the logic goes to gic_init_bases() and expects well
defined data to initialize GIC properly. The same solution
is used for GICv2 driver.
This is needed for ACPI initialization later.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/irqchip/irq-gic-v3.c | 105 +++++++++++++++++++++++++------------------
1 file changed, 61 insertions(+), 44 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5492f4e..19a65de 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -766,17 +766,69 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
.free = gic_irq_domain_free,
};
+static int __init gic_init_bases(void __iomem *dist_base,
+ struct redist_region *rdist_regs,
+ u32 nr_redist_regions,
+ u64 redist_stride,
+ void *domain_token)
+{
+ u32 typer;
+ int gic_irqs;
+ int err;
+
+ gic_data.dist_base = dist_base;
+ gic_data.redist_regions = rdist_regs;
+ gic_data.nr_redist_regions = nr_redist_regions;
+ gic_data.redist_stride = redist_stride;
+
+ /*
+ * Find out how many interrupts are supported.
+ * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
+ */
+ typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
+ gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
+ gic_irqs = GICD_TYPER_IRQS(typer);
+ if (gic_irqs > 1020)
+ gic_irqs = 1020;
+ gic_data.irq_nr = gic_irqs;
+
+ gic_data.domain = irq_domain_add_tree(domain_token, &gic_irq_domain_ops,
+ &gic_data);
+ gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
+
+ if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
+ err = -ENOMEM;
+ goto out_free;
+ }
+
+ set_handle_irq(gic_handle_irq);
+
+ if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
+ its_init(domain_token, &gic_data.rdists, gic_data.domain);
+
+ gic_smp_init();
+ gic_dist_init();
+ gic_cpu_init();
+ gic_cpu_pm_init();
+
+ return 0;
+
+out_free:
+ if (gic_data.domain)
+ irq_domain_remove(gic_data.domain);
+ free_percpu(gic_data.rdists.rdist);
+ return err;
+}
+
+#ifdef CONFIG_OF
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
{
void __iomem *dist_base;
struct redist_region *rdist_regs;
u64 redist_stride;
u32 nr_redist_regions;
- u32 typer;
u32 reg;
- int gic_irqs;
- int err;
- int i;
+ int err, i;
dist_base = of_iomap(node, 0);
if (!dist_base) {
@@ -820,47 +872,11 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
redist_stride = 0;
- gic_data.dist_base = dist_base;
- gic_data.redist_regions = rdist_regs;
- gic_data.nr_redist_regions = nr_redist_regions;
- gic_data.redist_stride = redist_stride;
+ err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
+ redist_stride, node);
+ if (!err)
+ return 0;
- /*
- * Find out how many interrupts are supported.
- * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
- */
- typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
- gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
- gic_irqs = GICD_TYPER_IRQS(typer);
- if (gic_irqs > 1020)
- gic_irqs = 1020;
- gic_data.irq_nr = gic_irqs;
-
- gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
- &gic_data);
- gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
-
- if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
- err = -ENOMEM;
- goto out_free;
- }
-
- set_handle_irq(gic_handle_irq);
-
- if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
- its_init(node, &gic_data.rdists, gic_data.domain);
-
- gic_smp_init();
- gic_dist_init();
- gic_cpu_init();
- gic_cpu_pm_init();
-
- return 0;
-
-out_free:
- if (gic_data.domain)
- irq_domain_remove(gic_data.domain);
- free_percpu(gic_data.rdists.rdist);
out_unmap_rdist:
for (i = 0; i < nr_redist_regions; i++)
if (rdist_regs[i].redist_base)
@@ -872,3 +888,4 @@ out_unmap_dist:
}
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
+#endif
--
1.9.1
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| From | Timur Tabi <timur@codeaurora.org> |
|---|---|
| Date | 2015-08-12 00:10 +0200 |
| Message-ID | <pWpU5-1pu-13@gated-at.bofh.it> |
| In reply to | #1195003 |
On 07/29/2015 05:08 AM, Hanjun Guo wrote: > Patches are on top of Marc's branch irq/gsi-irq-domain-v2, and available > at: > > git://git.linaro.org/leg/acpi/acpi.git gsi-irqdomain Is it my imagination, or is Marc's branch based on v3.9-rc7? Also, shouldn't this code be based on the upstream kernel, and not the LEG kernel? -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | G Gregory <graeme.gregory@linaro.org> |
|---|---|
| Date | 2015-08-12 00:30 +0200 |
| Subject | Re: [Linaro-acpi] [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support |
| Message-ID | <pWqds-1LO-13@gated-at.bofh.it> |
| In reply to | #1205456 |
On 11 August 2015 at 23:01, Timur Tabi <timur@codeaurora.org> wrote: > On 07/29/2015 05:08 AM, Hanjun Guo wrote: >> >> Patches are on top of Marc's branch irq/gsi-irq-domain-v2, and available >> at: >> >> git://git.linaro.org/leg/acpi/acpi.git gsi-irqdomain > > > Is it my imagination, or is Marc's branch based on v3.9-rc7? > Looks like 4.2-rc2 to me. > Also, shouldn't this code be based on the upstream kernel, and not the LEG > kernel? > Nothing LEG kernelly in there. Graeme -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-12 00:30 +0200 |
| Subject | Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support |
| Message-ID | <pWqds-1LO-15@gated-at.bofh.it> |
| In reply to | #1205456 |
On Tue, 11 Aug 2015 23:01:57 +0100 Timur Tabi <timur@codeaurora.org> wrote: > On 07/29/2015 05:08 AM, Hanjun Guo wrote: > > Patches are on top of Marc's branch irq/gsi-irq-domain-v2, and available > > at: > > > > git://git.linaro.org/leg/acpi/acpi.git gsi-irqdomain > > Is it my imagination, or is Marc's branch based on v3.9-rc7? That's definitely your imagination. I've stopped working on 3.9 over two years ago... > Also, shouldn't this code be based on the upstream kernel, and not the > LEG kernel? My branch, as far as I can tell by looking at my own git tree, is based on v4.2-rc2. As for "the LEG kernel", I have no idea what that is. I only work on this thing called "the Linux kernel". You may have heard of it! ;-) Thanks, M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Timur Tabi <timur@codeaurora.org> |
|---|---|
| Date | 2015-08-12 00:40 +0200 |
| Message-ID | <pWqn7-1X7-3@gated-at.bofh.it> |
| In reply to | #1205466 |
On 08/11/2015 05:25 PM, Marc Zyngier wrote:
> My branch, as far as I can tell by looking at my own git tree, is based
> on v4.2-rc2. As for "the LEG kernel", I have no idea what that is. I
> only work on this thing called "the Linux kernel". You may have heard
> of it!;-)
Then what is this:
git://git.linaro.org/leg/acpi/acpi.git
^^^
This is your tree, isn't it? Hanjun said, "Patches are on top of Marc's
branch irq/gsi-irq-domain-v2, and available at:
git://git.linaro.org/leg/acpi/acpi.git gsi-irqdomain".
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-12 00:50 +0200 |
| Subject | Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support |
| Message-ID | <pWqwO-28O-13@gated-at.bofh.it> |
| In reply to | #1205469 |
On Tue, 11 Aug 2015 23:36:14 +0100 Timur Tabi <timur@codeaurora.org> wrote: > On 08/11/2015 05:25 PM, Marc Zyngier wrote: > > My branch, as far as I can tell by looking at my own git tree, is based > > on v4.2-rc2. As for "the LEG kernel", I have no idea what that is. I > > only work on this thing called "the Linux kernel". You may have heard > > of it!;-) > > Then what is this: > > git://git.linaro.org/leg/acpi/acpi.git > ^^^ > > This is your tree, isn't it? My tree would have "maz" in it, and would rather be hosted on kernel.org. > Hanjun said, "Patches are on top of Marc's > branch irq/gsi-irq-domain-v2, and available at: > git://git.linaro.org/leg/acpi/acpi.git gsi-irqdomain". I don't see any contradiction here. Hanjun picked the patches from my own branch in my own tree, put his own patches on top, and pushed that out on an branch called gsi-irqdomain that is definitely based on 4.2-rc2. I have no idea where your 3.9-rc7 comes from. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Timur Tabi <timur@codeaurora.org> |
|---|---|
| Date | 2015-08-12 01:40 +0200 |
| Message-ID | <pWrjb-3iz-1@gated-at.bofh.it> |
| In reply to | #1205474 |
On 08/11/2015 05:48 PM, Marc Zyngier wrote: > I don't see any contradiction here. Hanjun picked the patches from my > own branch in my own tree, put his own patches on top, and pushed that > out on an branch called gsi-irqdomain that is definitely based on > 4.2-rc2. I have no idea where your 3.9-rc7 comes from. Ok, so that's not your kernel, but the LEG kernel instead. The top commits show this: Follows: tracking-mainline-llct-20130415.0, tracking-mainline-llct-20130417.0, v3.9-rc7 Also, $ git tag | grep v4 shows no v4.x tags. Anyway, I don't want to make a big deal about this. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2015-08-12 09:30 +0200 |
| Subject | Re: [PATCH v4 00/10] ACPI GIC Self-probing, GICv2m and GICv3 support |
| Message-ID | <pWyE2-5X6-25@gated-at.bofh.it> |
| In reply to | #1205501 |
On Wed, 12 Aug 2015 00:33:44 +0100 Timur Tabi <timur@codeaurora.org> wrote: > On 08/11/2015 05:48 PM, Marc Zyngier wrote: > > I don't see any contradiction here. Hanjun picked the patches from my > > own branch in my own tree, put his own patches on top, and pushed that > > out on an branch called gsi-irqdomain that is definitely based on > > 4.2-rc2. I have no idea where your 3.9-rc7 comes from. > > Ok, so that's not your kernel, but the LEG kernel instead. > > The top commits show this: > > Follows: tracking-mainline-llct-20130415.0, > tracking-mainline-llct-20130417.0, v3.9-rc7 > > Also, > $ git tag | grep v4 > > shows no v4.x tags. > > Anyway, I don't want to make a big deal about this. I just cloned this repository, and none of the branches I received have this as their top commit. I can only guess that you're looking at something else. Thanks, M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Timur Tabi <timur@codeaurora.org> |
|---|---|
| Date | 2015-08-12 21:30 +0200 |
| Message-ID | <pWJSO-5jh-5@gated-at.bofh.it> |
| In reply to | #1205664 |
On 08/12/2015 02:21 AM, Marc Zyngier wrote: > I just cloned this repository, and none of the branches I received have > this as their top commit. I can only guess that you're looking at > something else. It took me way too long, but I can see the v4.2-rc2 merge commit now. I blame sunspots for my poor git-fu. Sorry for all the noise. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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