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Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY

Started byRoger Quadros <rogerq@ti.com>
First post2015-08-04 10:20 +0200
Last post2015-08-04 17:50 +0200
Articles 3 — 3 participants

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  Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to  SATA PHY Roger Quadros <rogerq@ti.com> - 2015-08-04 10:20 +0200
    Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to  SATA PHY Tony Lindgren <tony@atomide.com> - 2015-08-04 10:50 +0200
      Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to  SATA PHY Kishon Vijay Abraham I <kishon@ti.com> - 2015-08-04 17:50 +0200

#1199512 — Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY

FromRoger Quadros <rogerq@ti.com>
Date2015-08-04 10:20 +0200
SubjectRe: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY
Message-ID<pTFC2-4PP-31@gated-at.bofh.it>
Tony,

On 17/07/15 16:47, Roger Quadros wrote:
> This register is required to be passed to the SATA PHY driver
> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Can you please Ack or pick this for -fixes.
Kishon has already picked patch 1 in this series. Thanks.

cheers,
-roger

> ---
>  arch/arm/boot/dts/dra7.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 8f1e25b..4a0718c 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -1140,6 +1140,7 @@
>  				ctrl-module = <&omap_control_sata>;
>  				clocks = <&sys_clkin1>, <&sata_ref_clk>;
>  				clock-names = "sysclk", "refclk";
> +				syscon-pllreset = <&scm_conf 0x3fc>;
>  				#phy-cells = <0>;
>  			};
>  
> 
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#1199533

FromTony Lindgren <tony@atomide.com>
Date2015-08-04 10:50 +0200
Message-ID<pTG53-5oC-7@gated-at.bofh.it>
In reply to#1199512
* Roger Quadros <rogerq@ti.com> [150804 01:22]:
> Tony,
> 
> On 17/07/15 16:47, Roger Quadros wrote:
> > This register is required to be passed to the SATA PHY driver
> > to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
> > 
> > Signed-off-by: Roger Quadros <rogerq@ti.com>
> 
> Can you please Ack or pick this for -fixes.
> Kishon has already picked patch 1 in this series. Thanks.

Best that Kishon takes both then:

Acked-by: Tony Lindgren <tony@atomide.com>
 
> > ---
> >  arch/arm/boot/dts/dra7.dtsi | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> > index 8f1e25b..4a0718c 100644
> > --- a/arch/arm/boot/dts/dra7.dtsi
> > +++ b/arch/arm/boot/dts/dra7.dtsi
> > @@ -1140,6 +1140,7 @@
> >  				ctrl-module = <&omap_control_sata>;
> >  				clocks = <&sys_clkin1>, <&sata_ref_clk>;
> >  				clock-names = "sysclk", "refclk";
> > +				syscon-pllreset = <&scm_conf 0x3fc>;
> >  				#phy-cells = <0>;
> >  			};
> >  
> > 
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#1200106

FromKishon Vijay Abraham I <kishon@ti.com>
Date2015-08-04 17:50 +0200
Message-ID<pTMDx-6sx-33@gated-at.bofh.it>
In reply to#1199533

On Tuesday 04 August 2015 02:11 PM, Tony Lindgren wrote:
> * Roger Quadros <rogerq@ti.com> [150804 01:22]:
>> Tony,
>>
>> On 17/07/15 16:47, Roger Quadros wrote:
>>> This register is required to be passed to the SATA PHY driver
>>> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
>>>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>
>> Can you please Ack or pick this for -fixes.
>> Kishon has already picked patch 1 in this series. Thanks.
> 
> Best that Kishon takes both then:
> 
> Acked-by: Tony Lindgren <tony@atomide.com>

merged, thanks.

-Kishon
>  
>>> ---
>>>  arch/arm/boot/dts/dra7.dtsi | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>> index 8f1e25b..4a0718c 100644
>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>> @@ -1140,6 +1140,7 @@
>>>  				ctrl-module = <&omap_control_sata>;
>>>  				clocks = <&sys_clkin1>, <&sata_ref_clk>;
>>>  				clock-names = "sysclk", "refclk";
>>> +				syscon-pllreset = <&scm_conf 0x3fc>;
>>>  				#phy-cells = <0>;
>>>  			};
>>>  
>>>
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