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Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll

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  Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div  register for mainpll santosh shilimkar <santosh.shilimkar@oracle.com> - 2015-07-31 17:40 +0200

#1197135 — Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll

Olof,

As discussed patch 1/2 is already made it via clock tree. Please
pick the subject fix for your upcoming fixes pull request.

On 5/29/2015 9:04 AM, Murali Karicheri wrote:
> All of the keystone devices have a separate register to hold post
> divider value for main pll clock. Currently the fixed-postdiv
> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
> use a value of 2 for this. Now that we have fixed this in the pll
> clock driver change the dt bindings for the same.
>
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> ---
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>


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