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| Started by | Yong Wu <yong.wu@mediatek.com> |
|---|---|
| First post | 2015-07-27 06:30 +0200 |
| Last post | 2015-07-27 06:30 +0200 |
| Articles | 1 — 1 participant |
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Re: [PATCH v3 5/6] iommu/mediatek: Add mt8173 IOMMU driver Yong Wu <yong.wu@mediatek.com> - 2015-07-27 06:30 +0200
| From | Yong Wu <yong.wu@mediatek.com> |
|---|---|
| Date | 2015-07-27 06:30 +0200 |
| Subject | Re: [PATCH v3 5/6] iommu/mediatek: Add mt8173 IOMMU driver |
| Message-ID | <pQId3-7Ap-5@gated-at.bofh.it> |
On Fri, 2015-07-24 at 17:55 +0100, Will Deacon wrote:
> On Fri, Jul 24, 2015 at 06:43:13AM +0100, Yong Wu wrote:
> > On Tue, 2015-07-21 at 15:59 +0100, Will Deacon wrote:
> > > On Thu, Jul 16, 2015 at 10:04:34AM +0100, Yong Wu wrote:
> > > > +static void mtk_iommu_tlb_flush_all(void *cookie)
> > > > +{
> > > > + struct mtk_iommu_domain *domain = cookie;
> > > > + void __iomem *base;
> > > > +
> > > > + base = domain->data->base;
> > > > + writel(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL);
> > > > + writel(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
> > >
> > > This needs to be synchronous, so you probably want to call
> > > mtk_iommu_tlb_sync at the end.
> >
> > From our spec, we have to wait until HW done after tlb flush range.
> > But it don't need wait after tlb flush all.
> > so It isn't necessary to add mtk_iommu_tlb_sync in tlb_flush_all here.
>
> Okey doke, but I'm surprised you don't need a subsequent DSB or read-back.
> What if the writel is buffered on the way to the IOMMU?
Then I change to this:
//==========
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL);
writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
dsb(ishst);
//===========
dsb or mb(). which one is better here?
>
> Will
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