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[PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention)

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  [PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention) Roger Quadros <rogerq@ti.com> - 2015-07-17 15:50 +0200
    [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes Roger Quadros <rogerq@ti.com> - 2015-07-17 15:50 +0200
      Re: [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove  redundant nodes Kishon Vijay Abraham I <kishon@ti.com> - 2015-07-21 07:20 +0200

#1186840 — [PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention)

Hi,

Implement workaround for SATA errata i783 (SATA Lockup After SATA DPLL Unlock/Relock)
so that we can now turn off sata_refclk to support suspend-to-ram without preventing
core-retention.

Depends on http://article.gmane.org/gmane.linux.ports.arm.omap/126670.

Changelog:
v3:
- used scm_conf node in dra7.dtsi for control register access.

v2:
- Fixed pcie disable_clocks. Addressed review comments.

cheers,
-roger

Roger Quadros (3):
  phy: ti-pipe3: i783 workaround for SATA lockup after dpll
    unlock/relock
  ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY
  ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes

 Documentation/devicetree/bindings/phy/ti-phy.txt | 16 +++++++
 arch/arm/boot/dts/dra7.dtsi                      | 20 ++++----
 drivers/phy/phy-ti-pipe3.c                       | 61 +++++++++++++++++++++---
 3 files changed, 80 insertions(+), 17 deletions(-)

-- 
2.1.4

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#1186842 — [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes

scm_conf1 maps the control register address space after the
padconf till the end.

Fix the scm_conf and pmx_core resource lengths. We need to add
4 bytes to include the last 32-bit register space.

Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
They are not used by anyone and no longer needed as they are
covered by scm_conf and scm_conf1.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 4a0718c..d07c34c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -141,7 +141,7 @@
 				dra7_pmx_core: pinmux@1400 {
 					compatible = "ti,dra7-padconf",
 						     "pinctrl-single";
-					reg = <0x1400 0x0464>;
+					reg = <0x1400 0x0468>;
 					#address-cells = <1>;
 					#size-cells = <0>;
 					#interrupt-cells = <1>;
@@ -149,6 +149,13 @@
 					pinctrl-single,register-width = <32>;
 					pinctrl-single,function-mask = <0x3fffffff>;
 				};
+
+				scm_conf1: scm_conf@1 {
+					compatible = "syscon";
+					reg = <0x1868 0x03e0>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -286,16 +293,6 @@
 				#thermal-sensor-cells = <1>;
 		};
 
-		dra7_ctrl_core: ctrl_core@4a002000 {
-			compatible = "syscon";
-			reg = <0x4a002000 0x6d0>;
-		};
-
-		dra7_ctrl_general: tisyscon@4a002e00 {
-			compatible = "syscon";
-			reg = <0x4a002e00 0x7c>;
-		};
-
 		sdma: dma-controller@4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;
-- 
2.1.4

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#1188672 — Re: [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes

Hi,

On Monday 20 July 2015 05:34 PM, Tero Kristo wrote:
> On 07/17/2015 04:47 PM, Roger Quadros wrote:
>> scm_conf1 maps the control register address space after the
>> padconf till the end.
>>
>> Fix the scm_conf and pmx_core resource lengths. We need to add
>> 4 bytes to include the last 32-bit register space.
>>
>> Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
>> They are not used by anyone and no longer needed as they are
>> covered by scm_conf and scm_conf1.
> 
> Looks like you are doing three things in this patch, maybe split it up 
> as such?
> 
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
>>   1 file changed, 8 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 4a0718c..d07c34c 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -141,7 +141,7 @@
>>   				dra7_pmx_core: pinmux@1400 {
>>   					compatible = "ti,dra7-padconf",
>>   						     "pinctrl-single";
>> -					reg = <0x1400 0x0464>;
>> +					reg = <0x1400 0x0468>;
>>   					#address-cells = <1>;
>>   					#size-cells = <0>;
>>   					#interrupt-cells = <1>;
>> @@ -149,6 +149,13 @@
>>   					pinctrl-single,register-width = <32>;
>>   					pinctrl-single,function-mask = <0x3fffffff>;
>>   				};
>> +
>> +				scm_conf1: scm_conf@1 {
> 
> Should be ... scm_conf@1868?
> 
> Are there any users for this area anyway? I don't think we should map 
> this area just for fun of it. Mostly it looks like this contains efuse 
> values for OPPs, which should be mapped from the OPP layer, not as a 
> generic syscon.

The last few registers are used for PCIe PHY and I'll be needing it for the
next version of my patch series.

Thanks
Kishon
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