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Re: [PATCH 0/9] Intel core misc PMUs support

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  Re: [PATCH 0/9] Intel core misc PMUs support Ingo Molnar <mingo@kernel.org> - 2015-07-17 13:40 +0200

#1186727 — Re: [PATCH 0/9] Intel core misc PMUs support

* kan.liang@intel.com <kan.liang@intel.com> wrote:

> From: Kan Liang <kan.liang@intel.com>
> 
> This patchkit intends to support Intel core misc PMUs. There are miscellaneous 
> free running (read-only) counters in core. Some new PMUs called core misc PMUs 
> are composed to include these counters. The counters include TSC, IA32_APERF, 
> IA32_MPERF, IA32_PPERF, SMI_COUNT, CORE_C*_RESIDENCY and PKG_C*_RESIDENCY. There 
> could be more in future platform.

Could you please do something like:

  s/perf_event_intel_core_misc.c/perf_event_x86/

and in general propagate it to a core perf x86 position?

This feature is not Intel specific per se, although the initial MSRs you are 
supporting are Intel specific (and that is fine).

Thanks,

	Ingo
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