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| Started by | Will Deacon <will.deacon@arm.com> |
|---|---|
| First post | 2015-07-13 14:40 +0200 |
| Last post | 2015-07-13 14:40 +0200 |
| Articles | 3 — 1 participant |
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[PATCH 0/5] Add generic support for relaxed atomics Will Deacon <will.deacon@arm.com> - 2015-07-13 14:40 +0200
[PATCH 3/5] asm-generic: add relaxed/acquire/release variants for atomic_long_t Will Deacon <will.deacon@arm.com> - 2015-07-13 14:40 +0200
[PATCH 4/5] lockref: remove homebrew cmpxchg64_relaxed macro definition Will Deacon <will.deacon@arm.com> - 2015-07-13 14:40 +0200
| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Date | 2015-07-13 14:40 +0200 |
| Subject | [PATCH 0/5] Add generic support for relaxed atomics |
| Message-ID | <pLLbz-50E-3@gated-at.bofh.it> |
Hello,
This patch series adds support for a family of relaxed atomics to the
kernel. More specifically:
- acquire/release/relaxed flavours of xchg, cmpxchg and {add,sub}_return
- atomic_read_acquire
- atomic_set_release
This came out of a separate patch series porting the (barrier-heavy)
qrwlock code to arm64. Rather than have arch-specific hooks littered
around the place, it makes more sense to define a core set of relaxed
atomics that can be used regardless of architecture.
For now, the definitions simply take on the existing (i.e. full-barrier)
semantics, but there is a direct mapping onto arm64 and even architectures
with explicit memory barrier instructions (e.g. powerpc, arm) can benefit,
as they do from the existing smp_load_acquire/smp_store_release macros.
The final patch is a proof-of-concept port of the qrwlock over to the
new atomics. It's based on some of the pending patches from me and Waiman,
so it won't apply to mainline but I think it illustrates the usage well
enough.
All feedback welcome,
Will
--->8
Will Deacon (5):
atomics: add acquire/release/relaxed variants of some atomic
operations
asm-generic: rework atomic-long.h to avoid bulk code duplication
asm-generic: add relaxed/acquire/release variants for atomic_long_t
lockref: remove homebrew cmpxchg64_relaxed macro definition
locking/qrwlock: make use of acquire/release/relaxed atomics
Documentation/atomic_ops.txt | 4 +-
include/asm-generic/atomic-long.h | 263 ++++++++++++++------------------------
include/asm-generic/qrwlock.h | 13 +-
include/linux/atomic.h | 140 ++++++++++++++++++++
kernel/locking/qrwlock.c | 12 +-
lib/lockref.c | 8 --
6 files changed, 248 insertions(+), 192 deletions(-)
--
2.1.4
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| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Date | 2015-07-13 14:40 +0200 |
| Subject | [PATCH 3/5] asm-generic: add relaxed/acquire/release variants for atomic_long_t |
| Message-ID | <pLLbA-50E-23@gated-at.bofh.it> |
| In reply to | #1182772 |
This patch adds atomic_long_t wrappers for the new relaxed atomic
operations.
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
include/asm-generic/atomic-long.h | 86 +++++++++++++++++++++++++++------------
include/linux/atomic.h | 10 ++---
2 files changed, 64 insertions(+), 32 deletions(-)
diff --git a/include/asm-generic/atomic-long.h b/include/asm-generic/atomic-long.h
index beaea541adfb..a94cbebbc33d 100644
--- a/include/asm-generic/atomic-long.h
+++ b/include/asm-generic/atomic-long.h
@@ -34,19 +34,69 @@ typedef atomic_t atomic_long_t;
#endif
-static inline long atomic_long_read(atomic_long_t *l)
-{
- ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l;
-
- return (long)ATOMIC_LONG_PFX(_read)(v);
+#define ATOMIC_LONG_READ_OP(mo) \
+static inline long atomic_long_read##mo(atomic_long_t *l) \
+{ \
+ ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l; \
+ \
+ return (long)ATOMIC_LONG_PFX(_read##mo)(v); \
}
+ATOMIC_LONG_READ_OP()
+ATOMIC_LONG_READ_OP(_acquire)
-static inline void atomic_long_set(atomic_long_t *l, long i)
-{
- ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l;
+#undef ATOMIC_LONG_READ_OP
- ATOMIC_LONG_PFX(_set)(v, i);
+#define ATOMIC_LONG_SET_OP(mo) \
+static inline void atomic_long_set##mo(atomic_long_t *l, long i) \
+{ \
+ ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l; \
+ \
+ ATOMIC_LONG_PFX(_set##mo)(v, i); \
+}
+ATOMIC_LONG_SET_OP()
+ATOMIC_LONG_SET_OP(_release)
+
+#undef ATOMIC_LONG_SET_OP
+
+#define ATOMIC_LONG_ADD_SUB_OP(op, mo) \
+static inline long \
+atomic_long_##op##_return##mo(long i, atomic_long_t *l) \
+{ \
+ ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l; \
+ \
+ return (long)ATOMIC_LONG_PFX(_##op##_return##mo)(i, v); \
}
+ATOMIC_LONG_ADD_SUB_OP(add,)
+ATOMIC_LONG_ADD_SUB_OP(add, _relaxed)
+ATOMIC_LONG_ADD_SUB_OP(add, _acquire)
+ATOMIC_LONG_ADD_SUB_OP(add, _release)
+ATOMIC_LONG_ADD_SUB_OP(sub,)
+ATOMIC_LONG_ADD_SUB_OP(sub, _relaxed)
+ATOMIC_LONG_ADD_SUB_OP(sub, _acquire)
+ATOMIC_LONG_ADD_SUB_OP(sub, _release)
+
+#undef ATOMIC_LONG_ADD_SUB_OP
+
+#define atomic_long_cmpxchg_relaxed(l, old, new) \
+ (ATOMIC_LONG_PFX(_cmpxchg_relaxed)((ATOMIC_LONG_PFX(_t) *)(l), \
+ (old), (new)))
+#define atomic_long_cmpxchg_acquire(l, old, new) \
+ (ATOMIC_LONG_PFX(_cmpxchg_acquire)((ATOMIC_LONG_PFX(_t) *)(l), \
+ (old), (new)))
+#define atomic_long_cmpxchg_release(l, old, new) \
+ (ATOMIC_LONG_PFX(_cmpxchg_release)((ATOMIC_LONG_PFX(_t) *)(l), \
+ (old), (new)))
+#define atomic_long_cmpxchg(l, old, new) \
+ (ATOMIC_LONG_PFX(_cmpxchg)((ATOMIC_LONG_PFX(_t) *)(l), (old), (new)))
+
+#define atomic_long_xchg_relaxed(v, new) \
+ (ATOMIC_LONG_PFX(_xchg_relaxed)((ATOMIC_LONG_PFX(_t) *)(v), (new)))
+#define atomic_long_xchg_acquire(v, new) \
+ (ATOMIC_LONG_PFX(_xchg_acquire)((ATOMIC_LONG_PFX(_t) *)(v), (new)))
+#define atomic_long_xchg_release(v, new) \
+ (ATOMIC_LONG_PFX(_xchg_release)((ATOMIC_LONG_PFX(_t) *)(v), (new)))
+#define atomic_long_xchg(v, new) \
+ (ATOMIC_LONG_PFX(_xchg)((ATOMIC_LONG_PFX(_t) *)(v), (new)))
static inline void atomic_long_inc(atomic_long_t *l)
{
@@ -104,20 +154,6 @@ static inline int atomic_long_add_negative(long i, atomic_long_t *l)
return ATOMIC_LONG_PFX(_add_negative)(i, v);
}
-static inline long atomic_long_add_return(long i, atomic_long_t *l)
-{
- ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l;
-
- return (long)ATOMIC_LONG_PFX(_add_return)(i, v);
-}
-
-static inline long atomic_long_sub_return(long i, atomic_long_t *l)
-{
- ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l;
-
- return (long)ATOMIC_LONG_PFX(_sub_return)(i, v);
-}
-
static inline long atomic_long_inc_return(atomic_long_t *l)
{
ATOMIC_LONG_PFX(_t) *v = (ATOMIC_LONG_PFX(_t) *)l;
@@ -141,9 +177,5 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
#define atomic_long_inc_not_zero(l) \
ATOMIC_LONG_PFX(_inc_not_zero)((ATOMIC_LONG_PFX(_t) *)(l))
-#define atomic_long_cmpxchg(l, old, new) \
- (ATOMIC_LONG_PFX(_cmpxchg)((ATOMIC_LONG_PFX(_t) *)(l), (old), (new)))
-#define atomic_long_xchg(v, new) \
- (ATOMIC_LONG_PFX(_xchg)((ATOMIC_LONG_PFX(_t) *)(v), (new)))
#endif /* _ASM_GENERIC_ATOMIC_LONG_H */
diff --git a/include/linux/atomic.h b/include/linux/atomic.h
index a78c3704cd51..a8b4c68790de 100644
--- a/include/linux/atomic.h
+++ b/include/linux/atomic.h
@@ -124,11 +124,6 @@ static inline void atomic_or(int i, atomic_t *v)
}
#endif /* #ifndef CONFIG_ARCH_HAS_ATOMIC_OR */
-#include <asm-generic/atomic-long.h>
-#ifdef CONFIG_GENERIC_ATOMIC64
-#include <asm-generic/atomic64.h>
-#endif
-
/*
* Relaxed variants of xchg, cmpxchg and some atomic operations.
*
@@ -268,4 +263,9 @@ static inline void atomic_or(int i, atomic_t *v)
#define xchg_release xchg
#endif
+#include <asm-generic/atomic-long.h>
+#ifdef CONFIG_GENERIC_ATOMIC64
+#include <asm-generic/atomic64.h>
+#endif
+
#endif /* _LINUX_ATOMIC_H */
--
2.1.4
--
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| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Date | 2015-07-13 14:40 +0200 |
| Subject | [PATCH 4/5] lockref: remove homebrew cmpxchg64_relaxed macro definition |
| Message-ID | <pLLbB-50E-39@gated-at.bofh.it> |
| In reply to | #1182772 |
cmpxchg64_relaxed is now defined by asm-generic/atomic.h, so we can remove our local definition from the lockref code. Signed-off-by: Will Deacon <will.deacon@arm.com> --- lib/lockref.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/lib/lockref.c b/lib/lockref.c index 494994bf17c8..5a92189ad711 100644 --- a/lib/lockref.c +++ b/lib/lockref.c @@ -4,14 +4,6 @@ #if USE_CMPXCHG_LOCKREF /* - * Allow weakly-ordered memory architectures to provide barrier-less - * cmpxchg semantics for lockref updates. - */ -#ifndef cmpxchg64_relaxed -# define cmpxchg64_relaxed cmpxchg64 -#endif - -/* * Note that the "cmpxchg()" reloads the "old" value for the * failure case. */ -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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