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[PATCH 0/3] J6/J6Eco: Add PM support to PCIe

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  [PATCH 0/3] J6/J6Eco: Add PM support to PCIe Kishon Vijay Abraham I <kishon@ti.com> - 2015-07-03 13:10 +0200
    [PATCH 2/3] PCI: host: pcie-designware: add support for suspend and resume Kishon Vijay Abraham I <kishon@ti.com> - 2015-07-03 13:10 +0200

#1176495 — [PATCH 0/3] J6/J6Eco: Add PM support to PCIe

This series adds PM support to pci-dra7xx so that PCI clocks can be disabled
during suspend and enabled back during resume without affecting
PCI functionality.

This series is dependent on [1] for proper PM functionality.

[1] -> http://newscentral.exsees.com/item/595269de5c35c59c386b91ce8efd9872-eedf6742bb6159c3b1a90625c4d43407

Kishon Vijay Abraham I (3):
  PCI: host: pci-dra7xx: Disable pm_runtime if get_sync failure
  PCI: host: pcie-designware: add support for suspend and resume
  PCI: host: pci-dra7xx: add pm support to pci dra7xx

 drivers/pci/host/pci-dra7xx.c      |   78 +++++++++++++++++++++++++++++++++++-
 drivers/pci/host/pcie-designware.c |   20 +++++++++
 drivers/pci/host/pcie-designware.h |    2 +
 3 files changed, 99 insertions(+), 1 deletion(-)

-- 
1.7.9.5

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#1176496 — [PATCH 2/3] PCI: host: pcie-designware: add support for suspend and resume

Certain platforms require MSE bit to be cleared to set the master
in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
Controller Master Standby Behavior advises to use the clearing
of the local MSE bit to set the master in standby. Without this
some of the clocks do not idle).

Cleared the MSE bit on suspend and enabled it back on resume.
This is required to get suspend/resume working.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/pci/host/pcie-designware.c |   20 ++++++++++++++++++++
 drivers/pci/host/pcie-designware.h |    2 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 69486be..cfb2bd6 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -811,6 +811,26 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
 }
 
+void dw_pcie_suspend_rc(struct pcie_port *pp)
+{
+	u32 val;
+
+	/* clear MSE */
+	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+	val &= ~PCI_COMMAND_MEMORY;
+	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
+void dw_pcie_resume_rc(struct pcie_port *pp)
+{
+	u32 val;
+
+	/* set MSE */
+	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+	val |= PCI_COMMAND_MEMORY;
+	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
 MODULE_DESCRIPTION("Designware PCIe host controller driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index d0bbd27..0df2dfa 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,5 +83,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
+void dw_pcie_suspend_rc(struct pcie_port *pp);
+void dw_pcie_resume_rc(struct pcie_port *pp);
 
 #endif /* _PCIE_DESIGNWARE_H */
-- 
1.7.9.5

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