Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1740540
| From | Manu Gautam <mgautam@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 06/17] phy: qcom-qmp: Move SERDES/PCS START after PHY reset |
| Date | 2017-09-27 11:10 +0200 |
| Message-ID | <uugvU-kx-37@gated-at.bofh.it> (permalink) |
| References | <uugvT-kx-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Driver is currently performing PHY reset after starting SERDES/PCS. As per hardware datasheet reset must be done before starting PHY. Hence, update the sequence. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> --- drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index aa27757..263cf50 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -882,12 +882,12 @@ static int qcom_qmp_phy_init(struct phy *phy) if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; mask = cfg->mask_pcs_ready; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Back to linux.kernel | Previous | Next | Find similar | Unroll thread
[PATCH v2 06/17] phy: qcom-qmp: Move SERDES/PCS START after PHY reset Manu Gautam <mgautam@codeaurora.org> - 2017-09-27 11:10 +0200
csiph-web