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[PATCH v2 07/10] arm: dts: mt7623: add iommmu and jpecdec nodes

From Ryder Lee <ryder.lee@mediatek.com>
Newsgroups linux.kernel
Subject [PATCH v2 07/10] arm: dts: mt7623: add iommmu and jpecdec nodes
Date 2017-09-26 04:10 +0200
Message-ID <utNtV-6AN-43@gated-at.bofh.it> (permalink)
References <utNtT-6AN-1@gated-at.bofh.it>
Organization linux.* mail to news gateway

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This patch adds iommu and jpecdec nodes for MT7623.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
 arch/arm/boot/dts/mt7623.dtsi | 74 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index ca672bd..c3ce0b0 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -20,6 +20,7 @@
 #include <dt-bindings/power/mt2701-power.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include <dt-bindings/reset/mt2701-resets.h>
 #include <dt-bindings/thermal/thermal.h>
 #include "skeleton64.dtsi"
@@ -273,6 +274,17 @@
 			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	smi_common: smi@1000c000 {
+		compatible = "mediatek,mt7623-smi-common",
+			     "mediatek,mt2701-smi-common";
+		reg = <0 0x1000c000 0 0x1000>;
+		clocks = <&infracfg CLK_INFRA_SMI>,
+			 <&mmsys CLK_MM_SMI_COMMON>,
+			 <&infracfg CLK_INFRA_SMI>;
+		clock-names = "apb", "smi", "async";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	pwrap: pwrap@1000d000 {
 		compatible = "mediatek,mt7623-pwrap",
 			     "mediatek,mt2701-pwrap";
@@ -304,6 +316,17 @@
 		reg = <0 0x10200100 0 0x1c>;
 	};
 
+	iommu: mmsys_iommu@10205000 {
+		compatible = "mediatek,mt7623-m4u",
+			     "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		#iommu-cells = <1>;
+	};
+
 	efuse: efuse@10206000 {
 		compatible = "mediatek,mt7623-efuse",
 			     "mediatek,mt8173-efuse";
@@ -669,6 +692,18 @@
 		#clock-cells = <1>;
 	};
 
+	larb0: larb@14010000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x14010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <0>;
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
+			 <&mmsys CLK_MM_SMI_LARB0>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	imgsys: syscon@15000000 {
 		compatible = "mediatek,mt7623-imgsys",
 			     "mediatek,mt2701-imgsys",
@@ -677,6 +712,33 @@
 		#clock-cells = <1>;
 	};
 
+	larb2: larb@15001000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x15001000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <2>;
+		clocks = <&imgsys CLK_IMG_SMI_COMM>,
+			 <&imgsys CLK_IMG_SMI_COMM>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+	};
+
+	jpegdec: jpegdec@15004000 {
+		compatible = "mediatek,mt7623-jpgdec",
+			     "mediatek,mt2701-jpgdec";
+		reg = <0 0x15004000 0 0x1000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
+			  <&imgsys CLK_IMG_JPGDEC>;
+		clock-names = "jpgdec-smi",
+			      "jpgdec";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+		mediatek,larb = <&larb2>;
+		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
+			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
+	};
+
 	vdecsys: syscon@16000000 {
 		compatible = "mediatek,mt7623-vdecsys",
 			     "mediatek,mt2701-vdecsys",
@@ -685,6 +747,18 @@
 		#clock-cells = <1>;
 	};
 
+	larb1: larb@16010000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x16010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <1>;
+		clocks = <&vdecsys CLK_VDEC_CKGEN>,
+			 <&vdecsys CLK_VDEC_LARB>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+	};
+
 	hifsys: syscon@1a000000 {
 		compatible = "mediatek,mt7623-hifsys",
 			     "mediatek,mt2701-hifsys",
-- 
1.9.1

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Thread

[PATCH v2 00/10] update MT7623 and MT2701 dts Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 03/10] arm: dts: mt2701: add display subsystem related nodes Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 06/10] arm: dts: mt7623: add subsystem clock controller nodes Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 09/10] arm: dts: mt7623: enable bananapi-r2 display function Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 04/10] arm: dts: mediatek: update audio node for mt2701 and mt7623 Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 05/10] arm: dts: mt7623: update pio, usb and crypto nodes Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
    Re: [PATCH v2 05/10] arm: dts: mt7623: update pio, usb and crypto  nodes Yingjoe Chen <yingjoe.chen@mediatek.com> - 2017-09-26 12:20 +0200
  [PATCH v2 02/10] arm: dts: mt2701: enable display pwm backlight Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 01/10] arm: dts: mt2701: add pwm backlight device node Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 07/10] arm: dts: mt7623: add iommmu and jpecdec nodes Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 08/10] arm: dts: mt7623: add display subsystem related nodes Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200
  [PATCH v2 10/10] arm: dts: mt7623: add PCIe related nodes Ryder Lee <ryder.lee@mediatek.com> - 2017-09-26 04:10 +0200

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