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[PATCH 1/2] perf/x86/intel/uncore: correct num_boxes for IIO and IRP

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From: Kan Liang <Kan.liang@intel.com>

There are 6 IIO/IRP boxes for CBDMA, PCIe0-2, MCP 0 and MCP 1
separately.
Correct the num_boxes.

Signed-off-by: Kan Liang <Kan.liang@intel.com>
---
 arch/x86/events/intel/uncore_snbep.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index db1fe37..a719681 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3462,7 +3462,7 @@ static struct intel_uncore_ops skx_uncore_iio_ops = {
 static struct intel_uncore_type skx_uncore_iio = {
 	.name			= "iio",
 	.num_counters		= 4,
-	.num_boxes		= 5,
+	.num_boxes		= 6,
 	.perf_ctr_bits		= 48,
 	.event_ctl		= SKX_IIO0_MSR_PMON_CTL0,
 	.perf_ctr		= SKX_IIO0_MSR_PMON_CTR0,
@@ -3492,7 +3492,7 @@ static const struct attribute_group skx_uncore_format_group = {
 static struct intel_uncore_type skx_uncore_irp = {
 	.name			= "irp",
 	.num_counters		= 2,
-	.num_boxes		= 5,
+	.num_boxes		= 6,
 	.perf_ctr_bits		= 48,
 	.event_ctl		= SKX_IRP0_MSR_PMON_CTL0,
 	.perf_ctr		= SKX_IRP0_MSR_PMON_CTR0,
-- 
2.7.4

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[PATCH 1/2] perf/x86/intel/uncore: correct num_boxes for IIO and IRP kan.liang@intel.com - 2017-09-11 19:20 +0200
  [PATCH 2/2] perf/x86/intel/uncore: support IIO freerunning counter for SKX kan.liang@intel.com - 2017-09-11 19:20 +0200
  [tip:x86/urgent] perf/x86/intel/uncore: Correct num_boxes for IIO  and IRP tip-bot for Kan Liang <tipbot@zytor.com> - 2017-09-25 12:50 +0200

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