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Groups > linux.kernel > #1725778
| From | Stefan Brüns <stefan.bruens@rwth-aachen.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 |
| Date | 2017-09-04 00:50 +0200 |
| Message-ID | <ulLSi-5Nr-17@gated-at.bofh.it> (permalink) |
| References | <ulLSh-5Nr-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
For the H3, the burst lengths field offsets in the channel configuration
register differs from earlier SoC generations.
Using the A31 register macros actually configured the H3 controller
do to bursts of length 1 always, which although working leads to higher
bus utilisation.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
---
drivers/dma/sun6i-dma.c | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 1d9b3be30d22..f1a139f0102f 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -68,13 +68,15 @@
#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f)
#define DMA_CHAN_CFG_SRC_IO_MODE BIT(5)
#define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5)
-#define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7)
+#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
+#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
#define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
#define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
#define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16)
#define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
-#define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16)
+#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
+#define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
#define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
#define DMA_CHAN_CUR_SRC 0x10
@@ -554,11 +556,17 @@ static int set_config(struct sun6i_dma_dev *sdev,
if (dst_width < 0)
return dst_width;
- *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
- DMA_CHAN_CFG_SRC_WIDTH(src_width) |
- DMA_CHAN_CFG_DST_BURST(dst_burst) |
+ *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |
DMA_CHAN_CFG_DST_WIDTH(dst_width);
+ if (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) {
+ *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
+ DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
+ } else {
+ *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |
+ DMA_CHAN_CFG_DST_BURST_A31(dst_burst);
+ }
+
return 0;
}
@@ -601,11 +609,17 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
DMA_CHAN_CFG_DST_LINEAR_MODE |
DMA_CHAN_CFG_SRC_LINEAR_MODE |
- DMA_CHAN_CFG_SRC_BURST(burst) |
DMA_CHAN_CFG_SRC_WIDTH(width) |
- DMA_CHAN_CFG_DST_BURST(burst) |
DMA_CHAN_CFG_DST_WIDTH(width);
+ if (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) {
+ v_lli->cfg |= DMA_CHAN_CFG_SRC_BURST_H3(burst) |
+ DMA_CHAN_CFG_DST_BURST_H3(burst);
+ } else {
+ v_lli->cfg |= DMA_CHAN_CFG_SRC_BURST_A31(burst) |
+ DMA_CHAN_CFG_DST_BURST_A31(burst);
+ }
+
sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
sun6i_dma_dump_lli(vchan, v_lli);
--
2.14.1
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[PATCH 00/10] dmaengine: sun6i: Fixes for H3/A83T, enable A64 Stefan Brüns <stefan.bruens@rwth-aachen.de> - 2017-09-04 00:50 +0200
[PATCH 01/10] dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3 Stefan Brüns <stefan.bruens@rwth-aachen.de> - 2017-09-04 00:50 +0200
Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3 André Przywara <andre.przywara@arm.com> - 2017-09-04 01:30 +0200
Re: [PATCH 01/10] dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-09-04 09:10 +0200
[PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Stefan Brüns <stefan.bruens@rwth-aachen.de> - 2017-09-04 00:50 +0200
Re: [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-09-04 10:00 +0200
Re: [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Brüns, Stefan <Stefan.Bruens@rwth-aachen.de> - 2017-09-04 16:50 +0200
[PATCH 09/10] arm64: allwinner: a64: Add device node for DMA controller Stefan Brüns <stefan.bruens@rwth-aachen.de> - 2017-09-04 00:50 +0200
[PATCH 08/10] dmaengine: sun6i: Add support for Allwinner A64 and compatibles Stefan Brüns <stefan.bruens@rwth-aachen.de> - 2017-09-04 00:50 +0200
Re: [PATCH 08/10] dmaengine: sun6i: Add support for Allwinner A64 and compatibles André Przywara <andre.przywara@arm.com> - 2017-09-04 01:50 +0200
Re: [PATCH 08/10] dmaengine: sun6i: Add support for Allwinner A64 and compatibles Stefan Bruens <stefan.bruens@rwth-aachen.de> - 2017-09-04 02:20 +0200
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