Re: [RESEND PATCH 2/2] arm64: allwinner: pine64: Enable spi0/spi1

From	Maxime Ripard <maxime.ripard@free-electrons.com>
Newsgroups	linux.kernel
Subject	Re: [RESEND PATCH 2/2] arm64: allwinner: pine64: Enable spi0/spi1
Date	2017-08-30 16:50 +0200
Message-ID	<ukctA-16f-25@gated-at.bofh.it> (permalink)
References	<ujVj4-7iA-7@gated-at.bofh.it> <ujVj4-7iA-9@gated-at.bofh.it>
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Hi Stefan,

On Tue, Aug 29, 2017 at 10:26:52PM +0200, Stefan Brüns wrote:
> The two spi channels/controllers are available on the PI-2 resp. Euler
> connector, enable both. Contrary to the Pi, the A64 SOC only supports
> one chip select, so the second chipselect is not available (though
> it can be emulated using gpio chipselect).
> 
> Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> index 827168bc22ed..f25274e8b3e0 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
> @@ -124,6 +124,14 @@
>  	status = "okay";
>  };
>  
> +&spi0 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +};

Anything on the Euler or PI connector is muxable to some other
function. We cannot enforce a default, since we can't know for sure
that all our users will use it that way (even though the majority
probably will). This is why you also have those nodes populated but
disabled for the uart for example in the pine64 DTS.

But in our case, there's not much to populate :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[RESEND PATCH 2/2] arm64: allwinner: pine64: Enable spi0/spi1 Stefan Brüns <stefan.bruens@rwth-aachen.de> - 2017-08-29 22:30 +0200
  Re: [RESEND PATCH 2/2] arm64: allwinner: pine64: Enable spi0/spi1 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-08-30 16:50 +0200

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