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[PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register

From Jerome Brunet <jbrunet@baylibre.com>
Newsgroups linux.kernel
Subject [PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register
Date 2017-08-28 16:40 +0200
Message-ID <ujtmO-6J9-37@gated-at.bofh.it> (permalink)
References <ujtd7-6G2-7@gated-at.bofh.it>
Organization linux.* mail to news gateway

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On boot, the clock divider value is 0 which is a weird unsupported value.
For example, accessing the cfg register with this value set would crash
the SoC.

Previous change removed 0 as possible value for CCF but forgot to properly
initialize the register before registering the clock. This leads to the
CCF finding an illegal value, which it complains about.

Initialize the register properly in a standalone patch so the fix can be
picked up if necessary

Fixes: d045fe8c27af ("mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag")
Reported-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 8a74a048db88..d2de5c11cdce 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -339,6 +339,15 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	const char *clk_div_parents[1];
 	u32 clk_reg, cfg;
 
+	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
+	clk_reg = 0;
+	clk_reg |= CLK_ALWAYS_ON;
+	clk_reg |= CLK_DIV_MASK;
+	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase);
+	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase);
+	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase);
+	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
+
 	/* get the mux parents */
 	for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
 		struct clk *clk;
@@ -393,16 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
 		return PTR_ERR(host->cfg_div_clk);
 
-	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
-	clk_reg = 0;
-	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase);
-	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase);
-	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase);
-	clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL);
-	clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX);
-	clk_reg &= ~CLK_ALWAYS_ON;
-	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
-
 	/* Ensure clock starts in "auto" mode, not "always on" */
 	cfg = readl(host->regs + SD_EMMC_CFG);
 	cfg &= ~CFG_CLK_ALWAYS_ON;
-- 
2.9.5

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Thread

[PATCH v3 00/13] mmc: meson-gx: driver fixups and upgrades Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:30 +0200
  [PATCH v3 11/13] mmc: meson-gx: implement voltage switch callback Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 03/13] mmc: meson-gx: rework set_ios function Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 12/13] mmc: meson-gx: change default tx phase Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 10/13] mmc: meson-gx: use CCF to handle the clock phases Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 05/13] mmc: meson-gx: rework clock init function Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 08/13] mmc: meson-gx: simplify interrupt handler Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 07/13] mmc: meson-gx: work around clk-stop issue Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 04/13] mmc: meson-gx: rework clk_set function Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 06/13] mmc: meson-gx: fix dual data rate mode frequencies Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  [PATCH v3 02/13] mmc: meson-gx: cfg init overwrite values Jerome Brunet <jbrunet@baylibre.com> - 2017-08-28 16:40 +0200
  Re: [PATCH v3 00/13] mmc: meson-gx: driver fixups and upgrades Ulf Hansson <ulf.hansson@linaro.org> - 2017-08-30 15:20 +0200
    Re: [PATCH v3 00/13] mmc: meson-gx: driver fixups and upgrades Kevin Hilman <khilman@baylibre.com> - 2017-08-30 21:10 +0200
      Re: [PATCH v3 00/13] mmc: meson-gx: driver fixups and upgrades Ulf Hansson <ulf.hansson@linaro.org> - 2017-08-31 12:50 +0200

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