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Groups > linux.kernel > #1720482
| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [patch V2 24/44] x86/fpu: Use bitfield accessors for desc_struct |
| Date | 2017-08-26 00:10 +0200 |
| Message-ID | <uiuXG-1gP-77@gated-at.bofh.it> (permalink) |
| References | <uiuNX-Yh-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
desc_struct is a union of u32 fields and bitfields. The access to the u32
fields is done with magic macros.
Convert it to use the bitfields and replace the macro magic with parseable
inline functions.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/math-emu/fpu_entry.c | 11 ++++-----
arch/x86/math-emu/fpu_system.h | 48 ++++++++++++++++++++++++++++++----------
arch/x86/math-emu/get_address.c | 17 +++++++-------
3 files changed, 51 insertions(+), 25 deletions(-)
--- a/arch/x86/math-emu/fpu_entry.c
+++ b/arch/x86/math-emu/fpu_entry.c
@@ -147,7 +147,7 @@ void math_emulate(struct math_emu_info *
}
code_descriptor = FPU_get_ldt_descriptor(FPU_CS);
- if (SEG_D_SIZE(code_descriptor)) {
+ if (code_descriptor.d) {
/* The above test may be wrong, the book is not clear */
/* Segmented 32 bit protected mode */
addr_modes.default_mode = SEG32;
@@ -155,11 +155,10 @@ void math_emulate(struct math_emu_info *
/* 16 bit protected mode */
addr_modes.default_mode = PM16;
}
- FPU_EIP += code_base = SEG_BASE_ADDR(code_descriptor);
- code_limit = code_base
- + (SEG_LIMIT(code_descriptor) +
- 1) * SEG_GRANULARITY(code_descriptor)
- - 1;
+ FPU_EIP += code_base = seg_get_base(&code_descriptor);
+ code_limit = seg_get_limit(&code_descriptor) + 1;
+ code_limit *= seg_get_granularity(&code_descriptor);
+ code_limit += code_base - 1;
if (code_limit < code_base)
code_limit = 0xffffffff;
}
--- a/arch/x86/math-emu/fpu_system.h
+++ b/arch/x86/math-emu/fpu_system.h
@@ -34,17 +34,43 @@ static inline struct desc_struct FPU_get
return ret;
}
-#define SEG_D_SIZE(x) ((x).b & (3 << 21))
-#define SEG_G_BIT(x) ((x).b & (1 << 23))
-#define SEG_GRANULARITY(x) (((x).b & (1 << 23)) ? 4096 : 1)
-#define SEG_286_MODE(x) ((x).b & ( 0xff000000 | 0xf0000 | (1 << 23)))
-#define SEG_BASE_ADDR(s) (((s).b & 0xff000000) \
- | (((s).b & 0xff) << 16) | ((s).a >> 16))
-#define SEG_LIMIT(s) (((s).b & 0xff0000) | ((s).a & 0xffff))
-#define SEG_EXECUTE_ONLY(s) (((s).b & ((1 << 11) | (1 << 9))) == (1 << 11))
-#define SEG_WRITE_PERM(s) (((s).b & ((1 << 11) | (1 << 9))) == (1 << 9))
-#define SEG_EXPAND_DOWN(s) (((s).b & ((1 << 11) | (1 << 10))) \
- == (1 << 10))
+#define SEG_TYPE_WRITABLE (1U << 1)
+#define SEG_TYPE_EXPANDS_DOWN (1U << 2)
+#define SEG_TYPE_EXECUTE (1U << 3)
+#define SEG_TYPE_EXPAND_MASK (SEG_TYPE_EXPANDS_DOWN | SEG_TYPE_EXECUTE)
+#define SEG_TYPE_EXECUTE_MASK (SEG_TYPE_WRITABLE | SEG_TYPE_EXECUTE)
+
+static inline unsigned long seg_get_base(struct desc_struct *d)
+{
+ unsigned long base = (unsigned long)d->base2 << 24;
+
+ return base | ((unsigned long)d->base1 << 16) | d->base0;
+}
+
+static inline unsigned long seg_get_limit(struct desc_struct *d)
+{
+ return ((unsigned long)d->limit << 16) | d->limit0;
+}
+
+static inline unsigned long seg_get_granularity(struct desc_struct *d)
+{
+ return d->g ? 4096 : 1;
+}
+
+static inline bool seg_expands_down(struct desc_struct *d)
+{
+ return (d->type & SEG_TYPE_EXPAND_MASK) == SEG_TYPE_EXPANDS_DOWN;
+}
+
+static inline bool seg_execute_only(struct desc_struct *d)
+{
+ return (d->type & SEG_TYPE_EXECUTE_MASK) == SEG_TYPE_EXECUTE;
+}
+
+static inline bool seg_writable(struct desc_struct *d)
+{
+ return (d->type & SEG_TYPE_EXECUTE_MASK) == SEG_TYPE_WRITABLE;
+}
#define I387 (¤t->thread.fpu.state)
#define FPU_info (I387->soft.info)
--- a/arch/x86/math-emu/get_address.c
+++ b/arch/x86/math-emu/get_address.c
@@ -159,17 +159,18 @@ static long pm_address(u_char FPU_modrm,
}
descriptor = FPU_get_ldt_descriptor(addr->selector);
- base_address = SEG_BASE_ADDR(descriptor);
+ base_address = seg_get_base(&descriptor);
address = base_address + offset;
- limit = base_address
- + (SEG_LIMIT(descriptor) + 1) * SEG_GRANULARITY(descriptor) - 1;
+ limit = seg_get_limit(&descriptor) + 1;
+ limit *= seg_get_granularity(&descriptor);
+ limit += base_address - 1;
if (limit < base_address)
limit = 0xffffffff;
- if (SEG_EXPAND_DOWN(descriptor)) {
- if (SEG_G_BIT(descriptor))
+ if (seg_expands_down(&descriptor)) {
+ if (descriptor.g) {
seg_top = 0xffffffff;
- else {
+ } else {
seg_top = base_address + (1 << 20);
if (seg_top < base_address)
seg_top = 0xffffffff;
@@ -182,8 +183,8 @@ static long pm_address(u_char FPU_modrm,
(address > limit) || (address < base_address) ? 0 :
((limit - address) >= 254 ? 255 : limit - address + 1);
}
- if (SEG_EXECUTE_ONLY(descriptor) ||
- (!SEG_WRITE_PERM(descriptor) && (FPU_modrm & FPU_WRITE_BIT))) {
+ if (seg_execute_only(&descriptor) ||
+ (!seg_writable(&descriptor) && (FPU_modrm & FPU_WRITE_BIT))) {
access_limit = 0;
}
return address;
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[patch V2 00/44] x86: Cleanup IDT code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 23/44] x86/percpu: Use static initializer for GDT entry Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 33/44] x86/idt: Move early IDT setup out of 32bit asm Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 44/44] x86/idt: Hide set_intr_gate() Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 38/44] x86/idt: Move regular trap init to tables Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 02/44] x86/irq: Unexport used_vectors Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 21/44] x86/tracing: Build tracepoints only when they are used Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 04/44] x86/irq: Remove duplicated used_vectors definition Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 39/44] x86/idt: Move APIC gate initialization to tables Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 11/44] x86/apic: Remove the duplicated tracing versions of interrupts Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:00 +0200
[patch V2 29/44] x86/idt: Move 32bit idt_descr to C code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 16/44] x86/idt: Remove tracing idt completely Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 05/44] x86/boot: Move EISA setup to a proper place Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 17/44] x86/idt: Cleanup the i386 low level entry macros Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 26/44] x86/gdt: Use bitfields for initialization Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 06/44] x86/tracing: Introduce a static key for exception tracing Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 18/44] x86/tracing: Disentangle pagefault and resched IPI tracing key Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 12/44] x86/irqwork: Get rid of duplicated tracing interrupt code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 20/44] x86/irq_work: Make it depend on APIC Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 09/44] x86/apic: Use this_cpu_ptr in local_timer_interrupt Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 27/44] x86/ldttss: Cleanup 32bit descriptors Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 13/44] x86/mce: Remove duplicated tracing interrupt code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 36/44] x86/idt: Move debug stack init to table based Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 15/44] x86/smp: Use static key for reschedule interrupt tracing Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 03/44] x86/irq: Get rid of the first_system_vector bogisity Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 14/44] x86/smp: Remove pointless duplicated interrupt code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 28/44] x86/idt: Create file for IDT related code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 07/44] x86/traps: Simplify pagefault tracing logic Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 37/44] x86/idt: Move ist stack based traps to table init Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 10/44] x86/irq: Get rid of duplicated trace_x86_platform_ipi() code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 31/44] x86/idt: Consolidate IDT invalidation Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 25/44] x86: Replace access to desc_struct:a/b fields Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
Re: [patch V2 25/44] x86: Replace access to desc_struct:a/b fields Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2017-08-26 04:20 +0200
[patch V2 34/44] x86/idt: Prepare for table based init Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 22/44] x86/idt: Unify gate_struct handling for 32/64bit Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 32/44] x86/idt: Move early IDT handler setup to IDT code Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 08/44] x86/apic: Remove the duplicated tracing version of local_timer_interrupt Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 30/44] x86/idt: Remove unused set_trap_gate() Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 24/44] x86/fpu: Use bitfield accessors for desc_struct Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:10 +0200
[patch V2 01/44] x86/irq: Remove vector_used_by_percpu_irq() Thomas Gleixner <tglx@linutronix.de> - 2017-08-26 00:20 +0200
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