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Groups > linux.kernel > #1718286
| From | "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCHv6 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time |
| Date | 2017-08-23 14:10 +0200 |
| Message-ID | <uhCDV-nu-49@gated-at.bofh.it> (permalink) |
| References | <uhCDT-nu-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
This patch prepare decompression code to boot-time switching between 4- and 5-level paging. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> --- arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index fbf4c32d0b62..2e362aea3319 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -347,6 +347,28 @@ preferred_addr: leaq boot_stack_end(%rbx), %rsp #ifdef CONFIG_X86_5LEVEL + /* Preserve rbx across cpuid */ + movq %rbx, %r8 + + /* Check if leaf 7 is supported */ + movl $0, %eax + cpuid + cmpl $7, %eax + jb lvl5 + + /* + * Check if la57 is supported. + * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16] + */ + movl $7, %eax + movl $0, %ecx + cpuid + andl $(1 << 16), %ecx + jz lvl5 + + /* Restore rbx */ + movq %r8, %rbx + /* Check if 5-level paging has already enabled */ movq %cr4, %rax testl $X86_CR4_LA57, %eax @@ -386,6 +408,8 @@ preferred_addr: pushq %rax lretq lvl5: + /* Restore rbx */ + movq %r8, %rbx #endif /* Zero EFLAGS */ -- 2.14.1
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[PATCHv6 00/19] Boot-time switching between 4- and 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 18/19] x86/mm: Redefine some of page table helpers as macros "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 11/19] x86/mm: Make STACK_TOP_MAX dynamic "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 03/19] x86/kasan: Use the same shadow offset for 4- and 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 05/19] x86/xen: Drop 5-level paging support code from XEN_PV code "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 12/19] x86/mm: Adjust virtual address space layout in early boot. "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 14/19] x86/mm: Fold p4d page table layer at runtime "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 02/19] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 09/19] x86/mm: Make MAX_PHYSADDR_BITS and MAX_PHYSMEM_BITS dynamic "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 17/19] x86/xen: Allow XEN_PV and XEN_PVH to be enabled with X86_5LEVEL "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200 [PATCHv6 04/19] x86/xen: Provide pre-built page tables only for XEN_PV and XEN_PVH "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-08-23 14:10 +0200
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