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Groups > linux.kernel > #1711318
| From | Casey Leedom <leedom@chelsio.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 |
| Date | 2017-08-14 20:10 +0200 |
| Message-ID | <uerYm-7s4-15@gated-at.bofh.it> (permalink) |
| References | <uepMR-5WA-9@gated-at.bofh.it> <uerYm-7s4-17@gated-at.bofh.it> <uerF0-76t-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
| From: Raj, Ashok <ashok.raj@intel.com>
| Sent: Monday, August 14, 2017 10:19 AM
|
| On Mon, Aug 14, 2017 at 11:44:57PM +0800, Ding Tianhong wrote:
| > Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe
| > Root Port where Upstream Transaction Layer Packets with the Relaxed
| > Ordering Attribute clear are allowed to bypass earlier TLPs with
| > Relaxed Ordering set, it would cause Data Corruption, so we need
| > to disable Relaxed Ordering Attribute when Upstream TLPs to the
| > Root Port.
| >
| > Signed-off-by: Casey Leedom <leedom@chelsio.com>
| > Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
| > Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>
| > Acked-by: Ashok Raj <ashok.raj@intel.com>
|
| I can't ack this patch :-).. must be someone from AMD. Please remove my
| signature from this.
You can go ahead and leave my name on since I'm the person who found and diagnosed the problem (with help from others inside Chelsio).
If anyone on the Linux PCI List knows anyone at AMD who'd be willing to respond it would be great, but as I noted earlier, I think that AMD has effectively abandoned the A1100 ("Seattle") ARM SoC, so I doubt if we'll get anyone from AMD to even comment now.
Casey
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[PATCH v10 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-08-14 17:50 +0200
[PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Ding Tianhong <dingtianhong@huawei.com> - 2017-08-14 18:10 +0200
Re: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 "Raj, Ashok" <ashok.raj@intel.com> - 2017-08-14 19:50 +0200
Re: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Casey Leedom <leedom@chelsio.com> - 2017-08-14 20:10 +0200
Re: [PATCH v10 3/5] PCI: Disable Relaxed Ordering Attributes for AMD A1100 Ding Tianhong <dingtianhong@huawei.com> - 2017-08-15 03:50 +0200
Re: [PATCH v10 0/5] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag David Miller <davem@davemloft.net> - 2017-08-14 20:20 +0200
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